Patents by Inventor Wenzhou XU

Wenzhou XU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240405151
    Abstract: An N-type double-sided solar cell preparation method comprises: sequentially forming a front aluminum oxide passivation layer and a front silicon nitride anti-reflection layer on a front face of an N-type silicon wafer. The front aluminum oxide passivation layer is prepared by using a plasma-enhanced atomic layer deposition method, and the deposition conditions thereof involve: any frequency in the frequency range of 40 kHz to 400 kHz is selected to be a radio-frequency power supply frequency, a gaseous aluminum source is first introduced into a plasma apparatus in a vacuum state, such that a layer of aluminum source molecules is adsorbed on the surface of the silicon wafer, and a gaseous oxygen source is then introduced, such that the oxygen source is ionized into plasma and reacts with the aluminum source to obtain aluminum oxide.
    Type: Application
    Filed: June 28, 2022
    Publication date: December 5, 2024
    Inventors: Wenzhou XU, Qian YAO, Guoqiang XING
  • Publication number: 20240395963
    Abstract: A method for manufacturing a TOPCon cell includes following steps: texturing a front side of an silicon wafer and then preparing a PN junction; forming a tunnel oxide layer, an intrinsic polysilicon layer, a doped polysilicon layer, and a silicon oxide mask layer in sequence on a back side of the silicon wafer, wherein the tunnel oxide layer is deposited by PEALD at a deposition temperature of 150° C. to 200° C., the doped polysilicon layer is deposited by PECVD, and the silicon oxide mask layer has a thickness of 10 nm to 40 nm; removing a wraparound silicon oxide mask layer material and a wraparound polysilicon layer material from the front side of the silicon wafer, and then removing the silicon oxide mask layer from the back side; and forming a front electrode on the PN junction and a back electrode on the doped polysilicon layer, respectively.
    Type: Application
    Filed: July 26, 2022
    Publication date: November 28, 2024
    Inventors: Wenzhou XU, Hao CHEN, Mingzhang DENG, Yu HE, Fan ZHOU, Guoqiang XING, Qian YAO
  • Publication number: 20240371633
    Abstract: In the preparation process for a passivated contact battery, preparation of a back surface field passivation structure thereof comprises: growing a tunneling oxide layer on a back surface of a silicon wafer; growing an intrinsic silicon carbide layer on a surface of the tunneling oxide layer; growing a phosphorus-doped silicon carbide layer on a surface of the intrinsic silicon carbide layer; and performing annealing, so as to cause the silicon carbide and the phosphorus in the phosphorus-doped silicon carbide layer to form covalent bonds. The passivated contact battery can be obtained by means of the described preparation process, and same comprises a silicon wafer as well as a tunneling oxide layer, an intrinsic silicon carbide layer, and a phosphorus-doped silicon carbide layer which are sequentially stacked on a back surface of the silicon wafer.
    Type: Application
    Filed: October 26, 2022
    Publication date: November 7, 2024
    Inventors: Hao CHEN, Wenzhou XU, Xiajie MENG, Qian YAO, Xiupeng WANG, GUOQIANG XING
  • Publication number: 20240258444
    Abstract: A silicon oxide layer is formed on the back surface of an N-type silicon wafer; an N-type silicon layer is formed on the silicon oxide layer, wherein the phosphine concentration of the N-type silicon layer is within a first preset concentration range; and an antireflection layer is formed on the N-type silicon layer and a back electrode is formed on the antireflection layer. In the high-temperature annealing process, hydrogen atoms can be bound by phosphine, such that membrane explosion caused by the escape of hydrogen atoms is avoided, an open-circuit voltage, the conversion efficiency and a filling factor can be improved, a back passivation effect can be enhanced, and the quality of a cell piece can be improved.
    Type: Application
    Filed: September 23, 2022
    Publication date: August 1, 2024
    Inventors: Wenzhou XU, Xiajie MENG, Qian YAO, Xiupeng WANG, GUOQIANG XING
  • Publication number: 20240186439
    Abstract: In a solar cell, the back surface of a substrate thereof is provided with alternately distributed emitter zones and back surface field zones. An emitter is formed in each emitter zone, and the emitters are made of boron-doped monocrystalline silicon. A back surface field is formed in each back surface field zone; the back surface fields comprise tunneling oxide layers and polycrystalline silicon layers in stacked distribution, the polycrystalline silicon layers being made of phosphorus-doped polycrystalline silicon, and the tunneling oxide layers being located between a polycrystalline silicon layer and a polycrystalline silicon layer. Positive electrodes are electrically connected to the emitters, and negative electrodes are electrically connected to the back surface fields.
    Type: Application
    Filed: May 30, 2022
    Publication date: June 6, 2024
    Inventors: Mingzhang DENG, Wenzhou XU, Yu HE, Hao CHEN, Fan ZHOU, Xiajie MENG, Pengyu ZHOU, Qian YAO, Guoqiang XING
  • Publication number: 20240145610
    Abstract: A tunnel oxide layer, an N-type bifacial crystalline silicon solar cell and a method for manufacturing the same are provided. The method for manufacturing the tunnel oxide layer includes forming excess -OH on a back side of a silicon wafer, and depositing the tunnel oxide layer on the back side of the silicon wafer by a Plasma Enhanced Atomic Layer Deposition method. The method for manufacturing the N-type bifacial crystalline silicon solar cell can include following steps: performing cleaning, texturing, boron diffusing, and alkaline polishing on an N-type silicon wafer, sequentially forming a P-type doped layer, a passivation layer, and an anti-reflection layer on a front side of the alkaline-polished N-type silicon wafer, and forming a tunnel oxide layer on a back side of the alkaline-polished N-type silicon wafer, followed by forming an N-type doped polysilicon layer, and after annealing, forming an anti-reflection layer.
    Type: Application
    Filed: July 27, 2022
    Publication date: May 2, 2024
    Inventors: Ming ZHANG, Xiajie MENG, Wenzhou XU, Hao CHEN, Mingzhang DENG, Guoqiang XING, Qian YAO