Abstract: A semiconductor device includes a substrate where an isolation region and an active region are defined, an anti-interference layer formed over the substrate in the isolation region, and a gate line simultaneously crossing the active region and the anti-interference layer.

Abstract: A semiconductor device includes a substrate where an isolation region and a plurality of active regions are defined, an anti-interference layer formed over the substrate in the isolation region, and a gate line simultaneously crossing the active region and the anti-interference layer.

Abstract: A fuse part in a semiconductor device includes a conductive pattern formed over a substrate, wherein the conductive pattern includes a blowing part and a pad part, making contact with both sides of the blowing part and having a larger thickness than that of the blowing part, a protection layer formed over the substrate having the conductive pattern, and a fuse box formed in the protection layer located on an upper portion of the blowing part, wherein a portion of the protection layer maintains a certain thickness over the blowing part.

Abstract: A method for fabricating a semiconductor device including forming a gate insulation layer, a conductive layer for a gate electrode, and an insulation layer for a gate hard mask over a substrate, selectively etching the insulation layer for a gate hard mask and the conductive layer for a gate electrode to expose a first region of the substrate, thereby forming an initial gate line, forming a first insulation layer for an insulation over a resultant structure where the initial gate line is formed, performing a planarization process until the insulation layer for a gate hard mask is exposed, and selectively etching the insulation layer for a gate hard mask and the conductive layer for a gate electrode to expose a second region of the substrate, the second region being not overlapped with the first region, thereby forming a final gate line having a line width smaller than the initial gate line.

Abstract: A semiconductor device includes a substrate where an isolation region and a plurality of active regions are defined, an anti-interference layer formed over the substrate in the isolation region, and a gate line simultaneously crossing the active region and the anti-interference layer.

Abstract: A method for fabricating a semiconductor device including forming a gate insulation layer, a conductive layer for a gate electrode, and an insulation layer for a gate hard mask over a substrate, selectively etching the insulation layer for a gate hard mask and the conductive layer for a gate electrode to expose a first region of the substrate, thereby forming an initial gate line, forming a first insulation layer for an insulation over a resultant structure where the initial gate line is formed, performing a planarization process until the insulation layer for a gate hard mask is exposed, and selectively etching the insulation layer for a gate hard mask and the conductive layer for a gate electrode to expose a second region of the substrate, the second region being not overlapped with the first region, thereby forming a final gate line having a line width smaller than the initial gate line.

Abstract: A method for fabricating a semiconductor device includes forming a gate insulation layer over a substrate, a first conductive layer over the gate insulation layer, and a second conductive layer over the first conductive layer, etching the second conductive layer to form a second gate electrode using a first mask pattern having a first width, forming an insulation layer over a resultant where the second gate electrode is formed, and etching the insulation layer, the first conductive layer and the gate insulation layer sequentially to form a gate using a second mask pattern having a second width greater than the first width, the gate including an etched gate insulation layer, a first gate electrode, the second gate electrode, and a gate hard mask, which are stacked in sequence, wherein both sidewalls and a top surface of the second gate electrode are covered with the gate hard mask.