Abstract: An integrated circuit includes first to third failure information storage units, an input selection unit suitable for alternately storing plural pieces of failure information in the first and second failure information storage units generated whenever each of a plurality of tests is performed on a device under test (DUT), and a storage selection unit suitable for relocating the plural pieces of failure information from the first or second failure information storage unit that was not selected by the input selection unit, to the third failure information storage unit while excluding overlapping failure information from relocating.

Abstract: An integrated circuit includes first to third failure information storage units, an input selection unit suitable for alternately storing plural pieces of failure information in the first and second failure information storage units generated whenever each of a plurality of tests is performed on a device under test (DUT), and a storage selection unit suitable for relocating the plural pieces of failure information from the first or second failure information storage unit that was not selected by the input selection unit, to the third failure information storage unit while excluding overlapping failure information from relocating.