Patents by Inventor Weon Taek NA

Weon Taek NA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Adaptive cache management based on programming model information
    Patent number: 11586539
    Abstract: A processing system selectively allocates space to store a group of one or more cache lines at a cache level of a cache hierarchy having a plurality of cache levels based on memory access patterns of a software application executing at the processing system. The processing system generates bit vectors indicating which cache levels are to allocate space to store groups of one or more cache lines based on the memory access patterns, which are derived from data granularity and movement information. Based on the bit vectors, the processing system provides hints to the cache hierarchy indicating the lowest cache level that can exploit the reuse potential for a particular data.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: February 21, 2023
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Weon Taek Na, Jagadish B. Kotra, Yasuko Eckert, Steven Raasch, Sergey Blagodurov
  • Using a bloom filter to reduce the number of memory addressees tracked by a coherence directory
    Patent number: 11226900
    Abstract: An approach for tracking data stored in caches uses a Bloom filter to reduce the number of addresses that need to be tracked by a coherence directory. When a requested address is determined to not be currently tracked by either the coherence directory or the Bloom filter, tracking of the address is initiated in the Bloom filter, but not in the coherence directory. Initiating tracking of the address in the Bloom filter includes setting hash bits in the Bloom filter so that subsequent requests for the address will “hit” the Bloom filter. When a requested address is determined to be tracked by the coherence directory, the Bloom filter is not used to track the address.
    Type: Grant
    Filed: January 29, 2020
    Date of Patent: January 18, 2022
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Weon Taek Na, Yasuko Eckert, Mark H. Oskin, Gabriel H. Loh, William Louie Walker, Michael Warren Boyer
  • USING A BLOOM FILTER TO REDUCE THE NUMBER OF MEMORY ADDRESSEES TRACKED BY A COHERENCE DIRECTORY
    Publication number: 20210232501
    Abstract: An approach for tracking data stored in caches uses a Bloom filter to reduce the number of addresses that need to be tracked by a coherence directory. When a requested address is determined to not be currently tracked by either the coherence directory or the Bloom filter, tracking of the address is initiated in the Bloom filter, but not in the coherence directory. Initiating tracking of the address in the Bloom filter includes setting hash bits in the Bloom filter so that subsequent requests for the address will “hit” the Bloom filter. When a requested address is determined to be tracked by the coherence directory, the Bloom filter is not used to track the address.
    Type: Application
    Filed: January 29, 2020
    Publication date: July 29, 2021
    Inventors: Weon Taek Na, Yasuko Eckert, Mark H. Oskin, Gabriel H. Loh, William Louie Walker, Michael Warren Boyer
  • ADAPTIVE CACHE MANAGEMENT BASED ON PROGRAMMING MODEL INFORMATION
    Publication number: 20210182193
    Abstract: A processing system selectively allocates space to store a group of one or more cache lines at a cache level of a cache hierarchy having a plurality of cache levels based on memory access patterns of a software application executing at the processing system. The processing system generates bit vectors indicating which cache levels are to allocate space to store groups of one or more cache lines based on the memory access patterns, which are derived from data granularity and movement information. Based on the bit vectors, the processing system provides hints to the cache hierarchy indicating the lowest cache level that can exploit the reuse potential for a particular data.
    Type: Application
    Filed: December 13, 2019
    Publication date: June 17, 2021
    Inventors: Weon Taek NA, Jagadish B. KOTRA, Yasuko ECKERT, Steven RAASCH, Sergey BLAGODUROV