Patents by Inventor Weon Wi Jang

Weon Wi Jang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8391057
    Abstract: A memory device includes a memory cell that includes a storage node, a first electrode, and a second electrode, the storage node stores an electrical charge, and the first electrode moves to connect to the storage node when the second electrode is energized.
    Type: Grant
    Filed: July 31, 2009
    Date of Patent: March 5, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Min-Sang Kim, Ji-Myoung Lee, Hyun-Jun Bae, Dong-Won Kim, Jun Seo, Yong-Hyun Kwon, Weon-Wi Jang, Keun-Hwi Cho
  • Patent number: 7787276
    Abstract: A method for controlling a memory array using a mechanical switch according to the present invention, in which the memory array comprises; a plurality of word lines; a plurality of bit lines intersecting each other with the plurality of word lines; a gate electrode connected to each of the word lines; a drain electrode spaced apart from the gate electrode and connected to a capacitor; and a source electrode comprises: an anchor part spaced apart from the gate electrode and connected to each of the bit lines; a mobile part where a dimple is formed, comprises the steps of: applying a first voltage V1 to the bit line selected from the plurality of bit lines; applying a second voltage V2 greater than a sum of the first voltage V1 and a pull-in voltage Vpi to the word lines selected from the plurality of word lines; and applying a voltage smaller than a sum of a erase voltage Verase and the pull-in voltage Vpi and a voltage greater than a difference between a write voltage Vwrite and the pull-in voltage Vpi to the
    Type: Grant
    Filed: May 16, 2008
    Date of Patent: August 31, 2010
    Assignee: Korea Advanced Institute of Science and Technology
    Inventors: Jun-Bo Yoon, Weon-Wi Jang, Jeong-Oen Lee
  • Publication number: 20100135064
    Abstract: A memory device includes a memory cell that includes a storage node, a first electrode, and a second electrode, the storage node stores an electrical charge, and the first electrode moves to connect to the storage node when the second electrode is energized.
    Type: Application
    Filed: July 31, 2009
    Publication date: June 3, 2010
    Inventors: Min-Sang Kim, Ji-Myoung Lee, Hyun-Jun Bae, Dong-Won Kim, Jun Seo, Yong-Hyun Kwon, Weon-Wi Jang, Keun-Hwi Cho
  • Publication number: 20100046079
    Abstract: The present invention relates to polymer patterns of various shapes formed using modifications of means and methods used in the prior lithography process, and the metal film patterns, metal patterns and plastic molds using the polymer patterns, as well as methods of forming these patterns and molds. The method of forming the polymer patterns comprises the steps of: (a) depositing a photosensitive polymer on the substrate to form a polymer film; (b) placing a photomask on the polymer film; and (c) irradiating the polymer film with a light moving in random direction through the photomask, so as to form at least one pattern which is concave from the surface of the polymer film in a direction perpendicular to the substrate and extends in a direction parallel to the substrate. The inventive polymer patterns have at least one pattern which is concave from the surface of the polymer film in a direction perpendicular to the substrate and extends in a direction parallel to the substrate.
    Type: Application
    Filed: February 4, 2005
    Publication date: February 25, 2010
    Inventors: Jun-Bo Yoon, Sung-il Chang, Dae-Hyun Kim, Hyung Suk Lee, Joon-Yong Choi, Weon-Wi Jang, Kyungho Lee
  • Publication number: 20090243063
    Abstract: Disclosed are a micro electro mechanical system (MEMS) device and a package thereof. The packaging method of a MEMS device comprises: sequentially forming a sacrificial layer, a support layer, and a block copolymer layer on a substrate on which the MEMS device is formed; self-assembling the block copolymer layer formed on the support layer; selectively etching a part of the self-assembled block copolymer layer to form a plurality of nano-pores; forming a plurality of etching holes in the support layer corresponding to the plurality of nano-pores using the block copolymer layer in which the plurality of nano-pores are formed as a mask; removing the sacrificial layer using the etching holes formed in the support layer; and forming a shielding layer on the support layer.
    Type: Application
    Filed: March 16, 2009
    Publication date: October 1, 2009
    Inventors: Jun-Bo Yoon, Byung-Kee Lee, Weon-Wi Jang
  • Patent number: 7486539
    Abstract: Provided are a memory array using a mechanical switch, a method for controlling the same, a display apparatus using a mechanical switch, and a method for controlling the same. The memory array comprises a plurality of word lines, a plurality of bit lines intersecting each other with the plurality of word lines, and a plurality of the mechanical switches. The mechanical switch comprises a gate electrode, a drain electrode, and a source electrode.
    Type: Grant
    Filed: November 3, 2006
    Date of Patent: February 3, 2009
    Assignee: Korea Advanced Instutute of Science & Technology
    Inventors: Weon Wi Jang, O-Deuk Kwon, Jeong Oen Lee, Jun-Bo Yoon
  • Publication number: 20090021972
    Abstract: A method for controlling a memory array using a mechanical switch according to the present invention, in which the memory array comprises; a plurality of word lines; a plurality of bit lines intersecting each other with the plurality of word lines; a gate electrode connected to each of the word lines; a drain electrode spaced apart from the gate electrode and connected to a capacitor; and a source electrode comprises: an anchor part spaced apart from the gate electrode and connected to each of the bit lines; a mobile part where a dimple is formed, comprises the steps of: applying a first voltage V1 to the bit line selected from the plurality of bit lines; applying a second voltage V2 greater than a sum of the first voltage V1 and a pull-in voltage Vpi to the word lines selected from the plurality of word lines; and applying a voltage smaller than a sum of a erase voltage Verase and the pull-in voltage Vpi and a voltage greater than a difference between a write voltage Vwrite and the pull-in voltage Vpi to the
    Type: Application
    Filed: May 16, 2008
    Publication date: January 22, 2009
    Inventors: Jun-Bo Yoon, Jeong-Oen Lee, Weon-Wi Jang