Abstract: In a nonvolatile memory device and a method for fabricating the same, a device comprises a substrate, a trench in the substrate and a first gate pattern comprising a first bottom gate electrode having a first portion in the trench and having a second portion on the first portion and protruding in an upward direction relative to an upper surface of the substrate. A second gate pattern comprising a second gate electrode is on the substrate at a side of the first gate pattern and insulated from the first gate pattern. An impurity region is present in the substrate at a side of the first gate pattern opposite the second gate pattern, and overlapping part of the trench.

Abstract: A method of preventing program-disturbances for a non-volatile semiconductor memory device having a plurality of memory cells of which each includes a selection transistor and a memory transistor coupled in series between a bit-line and a common source-line is provided. First non-selected memory cells that share a first selection-line with a selected memory cell, and second non-selected memory cells that do not share the first selection-line with the selected memory cell are determined when the selected memory cell is selected to be programmed among the memory cells. A negative voltage is applied to second selection-lines that are coupled to the second non-selected memory cells when the selected memory cell is programmed by applying a positive voltage to the first selection-line that is coupled to the selected memory cell.

Abstract: Semiconductor memory devices and methods of fabricating the semiconductor memory devices are provided, the semiconductor memory devices may include a one-time-programmable (OTP) cell and an electrically erasable programmable read-only memory (EEPROM). The OTP cell includes a memory transistor and a program transistor. The program transistor may include a fuse electrode and may be spaced apart from the memory transistor. The EEPROM cell includes a memory transistor including a first gate and a selection transistor including a second gate. The OTP cell includes a first high-density impurity region which overlaps with the fuse electrode.

Abstract: Provided is a method of forming an isolation structure of a semiconductor device capable of minimizing the number of performing a patterning process and having trenches of various depths. The method includes partially etching the semiconductor substrate using a first patterning process to form first trenches and second trenches having a first depth. The semiconductor substrate has first to third regions. The first trenches are formed in the first region, and the second trenched are formed in the second region. The semiconductor substrate is partially etched using a second patterning process, so that third trenches are formed in the third region, and fourth trenches are formed in the second region. The fourth trenches extend from bottoms of the second trenches. The third trenches have a second depth, and the fourth trenches have a third depth. An isolation layer filling the first to fourth trenches is formed.

Abstract: An electrically erasable and programmable read only memory (EEPROM) device and a method of manufacturing the EEPROM device are provided. First and second gate structures having the same structure are formed on a tunnel insulating layer formed on a substrate, such that the first and second gate structures are spaced apart from each other. A common source region is formed at a portion of the substrate located between the first and second gate structures. First and second drain regions are formed at first and second portions of the substrate adjacent to the first and second gate structures, respectively. Thus, the EEPROM device is manufactured including first and second transistors that have the same structure and may alternately serve as a memory transistor and a selection transistor according to an applied signal.

Abstract: A non-volatile memory device includes a semiconductor substrate having a first section including a substantially planar first top surface, a second section including a substantially planar second top surface, and a sidewall extending between the first and second top surfaces. The second top surface of the substrate is closer to a bottom surface of the substrate than is the first top surface. A charge storage pattern extends on the first and second top surfaces of the substrate and along the sidewall therebetween. A source region in the first section of the substrate extends from the first top surface into the second section of the substrate and has a stepped portion defined by the sidewall and the second top surface. Related fabrication methods and methods of operation are also discussed.

Abstract: A voltage supply device comprises: a charge pump configured to boost a power voltage and to supply the boosted power voltage to a output line; and a voltage control circuit configured to maintain a voltage level of the output line at a target voltage level; wherein the voltage control circuit comprises a reach-through element including a first region and a second region provided in a well, the reach-through element configured to control the voltage level of the output line, using a reach-through function between the first region and the second region.

Abstract: Provided is a method of forming an isolation structure of a semiconductor device capable of minimizing the number of performing a patterning process and having trenches of various depths. The method includes partially etching the semiconductor substrate using a first patterning process to form first trenches and second trenches having a first depth. The semiconductor substrate has first to third regions. The first trenches are formed in the first region, and the second trenched are formed in the second region. The semiconductor substrate is partially etched using a second patterning process, so that third trenches are formed in the third region, and fourth trenches are formed in the second region. The fourth trenches extend from bottoms of the second trenches. The third trenches have a second depth, and the fourth trenches have a third depth. An isolation layer filling the first to fourth trenches is formed.

Abstract: Semiconductor memory devices and methods of fabricating the semiconductor memory devices are provided, the semiconductor memory devices may include a one-time-programmable (OTP) cell and an electrically erasable programmable read-only memory (EEPROM). The OTP cell includes a memory transistor and a program transistor. The program transistor may include a fuse electrode and may be spaced apart from the memory transistor. The EEPROM cell includes a memory transistor including a first gate and a selection transistor including a second gate. The OTP cell includes a first high-density impurity region which overlaps with the fuse electrode.

Abstract: A device is described comprising a substrate of a first conductivity type having a first dopant concentration, a first well formed in the substrate, a second well of the first conductivity type formed in the substrate and being deeper than the first well, the second well having a higher dopant concentration than the first dopant concentration, and a nonvolatile memory cell formed on the second well. A device is described comprising four wells of various conductivity types with a nonvolatile memory cell formed on the second well. A device is described comprising a plurality of wells for isolating transistors of a plurality of voltage ranges, wherein each one of the plurality of wells contains at least one transistor of a particular voltage range, and wherein transistors of only one of the plurality of voltage ranges are within each of the plurality of wells.

Abstract: Provided are an EEPROM cell, an EEPROM device, and methods of manufacturing the EEPROM cell and the EEPROM device. The EEPROM cell is formed on a substrate including a first region and a second region. A first EEPROM device having a first select transistor and a first memory transistor is disposed in the first region, while a second EEPROM device having a second select transistor and a second memory transistor is disposed in the second region. In the first region, a first drain region and a second floating region are formed apart from each other. In the second region, a second drain region and a second floating region are formed apart from each other. A first impurity region, a second impurity region, and a third impurity region are disposed in a common source region between the first and second regions of the substrate. The first and third impurity regions form a DDD structure, and the first and second impurity region form an LDD structure.

Abstract: A gate structure in a semiconductor device includes a dielectric layer pattern on a substrate, a floating gate on the dielectric layer pattern, a gate mask on the floating gate, a tunnel insulation layer on the substrate, and a word line on the tunnel insulation layer. The dielectric layer pattern includes a first portion and a second portion having a thickness different from a thickness of the first portion. The floating gate includes a step and tips. The tunnel insulation layer makes contact with a sidewall of the floating gate. The word line extends on a portion of the gate mask.

Abstract: A voltage supply device comprises: a charge pump configured to boost a power voltage and to supply the boosted power voltage to a output line; and a voltage control circuit configured to maintain a voltage level of the output line at a target voltage level; wherein the voltage control circuit comprises a reach-through element including a first region and a second region provided in a well, the reach-through element configured to control the voltage level of the output line, using a reach-through function between the first region and the second region.

Abstract: In a nonvolatile semiconductor memory device, and a method of fabricating the same, the nonvolatile semiconductor memory device includes a cell doping region and source/drain regions in a semiconductor substrate, the cell doping region being doped as a first conductive type, a channel region disposed between the source/drain regions in the semiconductor substrate, a tunnel doping region of the first conductive type formed in a predetermined region of an upper portion of the cell doping region, the tunnel doping region being doped in a higher concentration than that of the cell doping region, a tunnel insulating layer formed on a surface of the semiconductor substrate on the tunnel doping region, a gate insulating layer surrounding the tunnel insulating layer and covering the channel region and the cell doping region exposed beyond the tunnel doping region, and a gate electrode covering the tunnel insulating layer and on the gate insulating layer.

Abstract: Provided are a flash memory device and a method of fabricating the same. The method includes forming a first dielectric layer on an active region of a semiconductor substrate. A first conductive layer is formed on the semiconductor substrate having the first dielectric layer. A mask pattern is formed on the first conductive layer. Using the mask pattern as an etch mask, the first conductive layer is etched to form a first conductive pattern narrowing from its upper surface toward its middle portion. A second dielectric layer is formed on the semiconductor substrate having the first conductive pattern. A second conductive pattern crossing the active region adjacent to the first conductive pattern and partially covering the first conductive pattern is formed on the semiconductor substrate having the second dielectric layer.

Abstract: A method of forming a tunneling insulating layer having a size smaller than the size obtained by the resolution of a photolithography process is provided. The method includes the steps of forming a first insulating layer and a second insulating layer on a substrate, forming a re-flowable material layer pattern to re-flow the re-flowable material layer pattern, removing the second insulating layer and the first insulating layer to expose the substrate, and forming a tunneling insulating layer.

Abstract: In a nonvolatile semiconductor memory device, and a method of fabricating the same, the nonvolatile semiconductor memory device includes a cell doping region and source/drain regions in a semiconductor substrate, the cell doping region being doped as a first conductive type, a channel region disposed between the source/drain regions in the semiconductor substrate, a tunnel doping region of the first conductive type formed in a predetermined region of an upper portion of the cell doping region, the tunnel doping region being doped in a higher concentration than that of the cell doping region, a tunnel insulating layer formed on a surface of the semiconductor substrate on the tunnel doping region, a gate insulating layer surrounding the tunnel insulating layer and covering the channel region and the cell doping region exposed beyond the tunnel doping region, and a gate electrode covering the tunnel insulating layer and on the gate insulating layer.

Abstract: There are provided EEPROM devices and methods of forming the same. The device includes: a substrate having an active region defined by a device isolation layer; a first sense line and a second sense line which straightly extend on the substrate and have a memory gate; a first word line and a second word line which extend to be parallel to the first sense line and the, second sense line at the substrate and have a select gate; and an isolation region which extends in a direction crossing an extension direction of the first sense line and the second sense line to parts of the first and second word lines, which discontinuously electrically isolates the memory gates, and which makes the select gate stepped.

Abstract: Example embodiments relate to a non-volatile memory device and a method of forming the same. A non-volatile memory device according to example embodiments may include a conductive pattern provided on the semiconductor substrate. A tunnel insulator may be provided on the conductive pattern. A memory gate structure may be provided on the semiconductor substrate so as to cover a first end of the conductive pattern. The first end may include an upward tapering, first protrusion. A select gate structure may be provided on the semiconductor substrate so as to cover the second end of the conductive pattern. The second end may include an upward tapering, second protrusion. The coverage of the first protrusion by the memory gate structure may be greater than the coverage of the second protrusion by the select gate structure.

Abstract: A non-volatile memory device includes a semiconductor substrate having a first section including a substantially planar first top surface, a second section including a substantially planar second top surface, and a sidewall extending between the first and second top surfaces. The second top surface of the substrate is closer to a bottom surface of the substrate than is the first top surface. A charge storage pattern extends on the first and second top surfaces of the substrate and along the sidewall therebetween. A source region in the first section of the substrate extends from the first top surface into the second section of the substrate and has a stepped portion defined by the sidewall and the second top surface. Related fabrication methods and methods of operation are also discussed.