Patents by Inventor Weon-Hong Kim
Weon-Hong Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11949012Abstract: A semiconductor device including: a first transistor which include a first gate stack on a substrate; and a second transistor which includes a second gate stack on the substrate, wherein the first gate stack includes a first ferroelectric material layer disposed on the substrate, a first work function layer disposed on the first ferroelectric material layer and a first upper gate electrode disposed on the first work function layer, wherein the second gate stack includes a second ferroelectric material layer disposed on the substrate, a second work function layer disposed on the second ferroelectric material layer and a second upper gate electrode disposed on the second work function layer, wherein the first work function layer includes the same material as the second work function layer, and wherein an effective work function of the first gate stack is different from an effective work function of the second gate stack.Type: GrantFiled: December 8, 2020Date of Patent: April 2, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jong Ho Park, Wan Don Kim, Weon Hong Kim, Hyeon Jun Baek, Byoung Hoon Lee, Jeong Hyuk Yim, Sang Jin Hyun
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Publication number: 20230071440Abstract: Inventive concepts relate to a semiconductor memory device. The semiconductor memory device comprising, a substrate comprising an NMOS region and a PMOS region, a first gate pattern the NMOS region of the substrate, and a second gate pattern disposed on the PMOS region of the substrate. The first gate pattern comprises a first high-k layer, a diffusion mitigation pattern, an N-type work function pattern, and a first gate electrode, which are sequentially stacked on the substrate, the second gate pattern comprises a second high-k layer and a second gate electrode which are sequentially stacked on the substrate, the diffusion mitigation pattern is in contact with the first high-k layer, a stacked structure of the first gate electrode is the same as that of the second gate electrode, and the second gate pattern does not comprise the N-type work function pattern.Type: ApplicationFiled: May 5, 2022Publication date: March 9, 2023Applicant: Samsung Electronics Co., Ltd.Inventors: Ah Rang CHOI, Chan-Sic YOON, Jung-Hoon HAN, Gyu Hyun KIL, Weon Hong KIM, Doo San BACK
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Publication number: 20210119058Abstract: A semiconductor device including: a first transistor which include a first gate stack on a substrate; and a second transistor which includes a second gate stack on the substrate, wherein the first gate stack includes a first ferroelectric material layer disposed on the substrate, a first work function layer disposed on the first ferroelectric material layer and a first upper gate electrode disposed on the first work function layer, wherein the second gate stack includes a second ferroelectric material layer disposed on the substrate, a second work function layer disposed on the second ferroelectric material layer and a second upper gate electrode disposed on the second work function layer, wherein the first work function layer includes the same material as the second work function layer, and wherein an effective work function of the first gate stack is different from an effective work function of the second gate stack.Type: ApplicationFiled: December 8, 2020Publication date: April 22, 2021Inventors: Jong Ho PARK, Wan Don KIM, Weon Hong KIM, Hyeon Jun BAEK, Byoung Hoon LEE, Jeong Hyuk YIM, Sang Jin HYUN
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Patent number: 10879392Abstract: A semiconductor device including: a first transistor which include a first gate stack on a substrate; and a second transistor which includes a second gate stack on the substrate, wherein the first gate stack includes a first ferroelectric material layer disposed on the substrate, a first work function layer disposed on the first ferroelectric material layer and a first upper gate electrode disposed on the first work function layer, wherein the second gate stack includes a second ferroelectric material layer disposed on the substrate, a second work function layer disposed on the second ferroelectric material layer and a second upper gate electrode disposed on the second work function layer, wherein the first work function layer includes the same material as the second work function layer, and wherein an effective work function of the first gate stack is different from an effective work function of the second gate stack.Type: GrantFiled: June 25, 2019Date of Patent: December 29, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jong Ho Park, Wan Don Kim, Weon Hong Kim, Hyeon Jun Baek, Byoung Hoon Lee, Jeong Hyuk Yim, Sang Jin Hyun
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Publication number: 20200013897Abstract: A semiconductor device including: a first transistor which include a first gate stack on a substrate; and a second transistor which includes a second gate stack on the substrate, wherein the first gate stack includes a first ferroelectric material layer disposed on the substrate, a first work function layer disposed on the first ferroelectric material layer and a first upper gate electrode disposed on the first work function layer, wherein the second gate stack. includes a second ferroelectric material layer disposed on the substrate, a second work function layer disposed on the second ferroelectric material layer and a second upper gate electrode disposed on the second work function layer, wherein the first work function layer includes the same material as the second work function layer, and wherein an effective work function of the first gate stack is different from an effective work function of the second gate stack.Type: ApplicationFiled: June 25, 2019Publication date: January 9, 2020Inventors: JONG HO PARK, Wan Don KIM, Weon Hong KIM, Hyeon Jun BAEK, Byoung Hoon LEE, Jeong Hyuk YIM, Sang Jin HYUN
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Patent number: 10312341Abstract: An integrated circuit device includes a first gate stack formed on a first high dielectric layer and comprising a first work function adjustment metal containing structure and a second gate stack formed on a second high dielectric layer and comprising a second work function adjustment metal containing structure having an oxygen content that is greater than that of the first work function adjustment metal containing structure.Type: GrantFiled: November 28, 2017Date of Patent: June 4, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ha-jin Lim, Gi-gwan Park, Weon-hong Kim
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Publication number: 20180090585Abstract: An integrated circuit device includes a first gate stack formed on a first high dielectric layer and comprising a first work function adjustment metal containing structure and a second gate stack formed on a second high dielectric layer and comprising a second work function adjustment metal containing structure having an oxygen content that is greater than that of the first work function adjustment metal containing structure.Type: ApplicationFiled: November 28, 2017Publication date: March 29, 2018Inventors: Ha-jin LIM, Gi-gwan PARK, Weon-hong KIM
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Patent number: 9922879Abstract: An integrated circuit device may include a gate insulation layer covering a top surface and opposite sidewalls of a fin-shaped active region, a gate electrode covering the gate insulation layer and a hydrogen atomic layer disposed along an interface between the fin-shaped active region and the gate insulation layer. A method of manufacturing the integrated circuit device may include forming an insulating layer covering a lower portion of a preliminary fin-shaped active region, forming a fin-shaped active region having an outer surface with an increased smoothness through annealing an upper portion of the preliminary fin-shaped active region in a hydrogen atmosphere and forming a hydrogen atomic layer covering the outer surface of the fin-shaped active region. A gate insulation layer and a gate electrode may be formed to cover a top surface and opposite sidewalls of the fin-shaped active region.Type: GrantFiled: September 8, 2017Date of Patent: March 20, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Weon-hong Kim, Dong-su Yoo, Min-joo Lee, Moon-kyun Song, Soo-jung Choi
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Patent number: 9859392Abstract: An integrated circuit device includes a first gate stack formed on a first high dielectric layer and comprising a first work function adjustment metal containing structure and a second gate stack formed on a second high dielectric layer and comprising a second work function adjustment metal containing structure having an oxygen content that is greater than that of the first work function adjustment metal containing structure.Type: GrantFiled: September 19, 2016Date of Patent: January 2, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ha-jin Lim, Gi-gwan Park, Weon-hong Kim
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Publication number: 20170372971Abstract: An integrated circuit device may include a gate insulation layer covering a top surface and opposite sidewalls of a fin-shaped active region, a gate electrode covering the gate insulation layer and a hydrogen atomic layer disposed along an interface between the fin-shaped active region and the gate insulation layer. A method of manufacturing the integrated circuit device may include forming an insulating layer covering a lower portion of a preliminary fin-shaped active region, forming a fin-shaped active region having an outer surface with an increased smoothness through annealing an upper portion of the preliminary fin-shaped active region in a hydrogen atmosphere and forming a hydrogen atomic layer covering the outer surface of the fin-shaped active region. A gate insulation layer and a gate electrode may be formed to cover a top surface and opposite sidewalls of the fin-shaped active region.Type: ApplicationFiled: September 8, 2017Publication date: December 28, 2017Inventors: Weon-hong KIM, Dong-su YOO, Min-joo LEE, Moon-kyun SONG, Soo-jung CHOI
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Patent number: 9779996Abstract: An integrated circuit device may include a gate insulation layer covering a top surface and opposite sidewalls of a fin-shaped active region, a gate electrode covering the gate insulation layer and a hydrogen atomic layer disposed along an interface between the fin-shaped active region and the gate insulation layer. A method of manufacturing the integrated circuit device may include forming an insulating layer covering a lower portion of a preliminary fin-shaped active region, forming a fin-shaped active region having an outer surface with an increased smoothness through annealing an upper portion of the preliminary fin-shaped active region in a hydrogen atmosphere and forming a hydrogen atomic layer covering the outer surface of the fin-shaped active region. A gate insulation layer and a gate electrode may be formed to cover a top surface and opposite sidewalls of the fin-shaped active region.Type: GrantFiled: May 12, 2016Date of Patent: October 3, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Weon-hong Kim, Dong-su Yoo, Min-Joo Lee, Moon-Kyun Song, Soo-jung Choi
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Patent number: 9702041Abstract: An apparatus and method for fabricating a semiconductor device using a 4-way valve with improved purge efficiency by improving a gas valve system by preventing dead volume from occurring are provided. The apparatus includes a reaction chamber in which a substrate is processed to fabricate a semiconductor device; a first processing gas supply pipe supplying a first processing gas into the reaction chamber; a 4-way valve having a first inlet, a second inlet, a first outlet, and a second outlet and installed at the first processing gas supply pipe such that the first inlet and the first outlet are connected to the first processing gas supply pipe; a second processing gas supply pipe connected to the second inlet of the 4-way valve to supply a second processing gas; a bypass connected to the second outlet of the 4-way valve; and a gate valve installed at the bypass.Type: GrantFiled: June 8, 2016Date of Patent: July 11, 2017Assignees: SAMSUNG ELECTRONICS CO., LTD., GENITECH, INC.Inventors: Seok-jun Won, Yong-min Yoo, Dae-youn Kim, Young-hoon Kim, Dae-jin Kwon, Weon-hong Kim
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Patent number: 9698021Abstract: In a method of forming a layer, a substrate is loaded into a chamber and placed at a home position that is a first relative angular position. A process cycle is performed a number of times while the substrate is at the home position. The cycle includes directing source gas onto the substrate at a first location adjacent the periphery of the substrate, purging the chamber, directing reaction gas onto the substrate from the first location, and purging the chamber. The cycle is performed another number of times while the substrate is at another relative angular position, i.e., at a position rotated about its general center relative from the home position.Type: GrantFiled: December 15, 2015Date of Patent: July 4, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Min-Joo Lee, Weon-Hong Kim, Moon-Kyun Song, Dong-Su Yoo, Soo-Jung Choi
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Publication number: 20170084711Abstract: An integrated circuit device includes a first gate stack formed on a first high dielectric layer and comprising a first work function adjustment metal containing structure and a second gate stack formed on a second high dielectric layer and comprising a second work function adjustment metal containing structure having an oxygen content that is greater than that of the first work function adjustment metal containing structure.Type: ApplicationFiled: September 19, 2016Publication date: March 23, 2017Inventors: Ha-jin LIM, Gi-gwan PARK, Weon-hong KIM
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Patent number: 9583592Abstract: In a method of manufacturing a semiconductor device, a dummy gate structure is formed on a substrate. A first spacer layer is formed on the substrate to cover the dummy gate structure. A nitridation process is performed on the first spacer layer. An upper portion of the substrate adjacent to the dummy gate structure is removed to form a trench. An inner wall of the trench is cleaned. An epitaxial layer is formed to fill the trench. The dummy gate structure is replaced with a gate structure.Type: GrantFiled: April 27, 2015Date of Patent: February 28, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Pan-Kwi Park, Dong-Suk Shin, Seok-Jun Won, Weon-Hong Kim, Jae-Gon Lee
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Publication number: 20170033013Abstract: An integrated circuit device may include a gate insulation layer covering a top surface and opposite sidewalls of a fin-shaped active region, a gate electrode covering the gate insulation layer and a hydrogen atomic layer disposed along an interface between the fin-shaped active region and the gate insulation layer. A method of manufacturing the integrated circuit device may include forming an insulating layer covering a lower portion of a preliminary fin-shaped active region, forming a fin-shaped active region having an outer surface with an increased smoothness through annealing an upper portion of the preliminary fin-shaped active region in a hydrogen atmosphere and forming a hydrogen atomic layer covering the outer surface of the fin-shaped active region. A gate insulation layer and a gate electrode may be formed to cover a top surface and opposite sidewalls of the fin-shaped active region.Type: ApplicationFiled: May 12, 2016Publication date: February 2, 2017Inventors: Weon-hong Kim, Dong-su Yoo, Min-Joo Lee, Moon-Kyun Song, Soo-jung Choi
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Publication number: 20160281234Abstract: An apparatus and method for fabricating a semiconductor device using a 4-way valve with improved purge efficiency by improving a gas valve system by preventing dead volume from occurring are provided. The apparatus includes a reaction chamber in which a substrate is processed to fabricate a semiconductor device; a first processing gas supply pipe supplying a first processing gas into the reaction chamber; a 4-way valve having a first inlet, a second inlet, a first outlet, and a second outlet and installed at the first processing gas supply pipe such that the first inlet and the first outlet are connected to the first processing gas supply pipe; a second processing gas supply pipe connected to the second inlet of the 4-way valve to supply a second processing gas; a bypass connected to the second outlet of the 4-way valve; and a gate valve installed at the bypass.Type: ApplicationFiled: June 8, 2016Publication date: September 29, 2016Applicants: SAMSUNG ELECTRONICS CO., LTD., GENITECH, INC.Inventors: Seok-jun WON, Yong-min YOO, Dae-youn KIM, Young-hoon KIM, Dae-jin KWON, Weon-hong KIM
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Patent number: 9431515Abstract: Methods of forming semiconductor devices are provided. A method of forming a semiconductor device includes forming an insulating layer that includes a trench therein. The method includes forming a high-k layer in the trench. Moreover, the method includes forming a metal layer on the high-k layer, then performing a first heat treatment at a first temperature, and performing a second heat treatment at a second temperature that is higher than the first temperature.Type: GrantFiled: March 6, 2015Date of Patent: August 30, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Seok-Jun Won, Weon-Hong Kim, Moon-Kyun Song
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Patent number: 9406502Abstract: An apparatus and method for fabricating a semiconductor device using a 4-way valve with improved purge efficiency by improving a gas valve system by preventing dead volume from occurring are provided. The apparatus includes a reaction chamber in which a substrate is processed to fabricate a semiconductor device; a first processing gas supply pipe supplying a first processing gas into the reaction chamber; a 4-way valve having a first inlet, a second inlet, a first outlet, and a second outlet and installed at the first processing gas supply pipe such that the first inlet and the first outlet are connected to the first processing gas supply pipe; a second processing gas supply pipe connected to the second inlet of the 4-way valve to supply a second processing gas; a bypass connected to the second outlet of the 4-way valve; and a gate valve installed at the bypass.Type: GrantFiled: April 14, 2015Date of Patent: August 2, 2016Assignees: SAMSUNG ELECTRONICS CO., LTD., GENITECH, INC.Inventors: Seok-jun Won, Yong-min Yoo, Dae-youn Kim, Young-hoon Kim, Dae-jin Kwon, Weon-hong Kim
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Publication number: 20160189951Abstract: In a method of forming a layer, a substrate is loaded into a chamber and placed at a home position that is a first relative angular position. A process cycle is performed a number of times while the substrate is at the home position. The cycle includes directing source gas onto the substrate at a first location adjacent the periphery of the substrate, purging the chamber, directing reaction gas onto the substrate from the first location, and purging the chamber. The cycle is performed another number of times while the substrate is at another relative angular position, i.e., at a position rotated about its general center relative from the home position.Type: ApplicationFiled: December 15, 2015Publication date: June 30, 2016Inventors: MIN-JOO LEE, WEON-HONG KIM, MOON-KYUN SONG, DONG-SU YOO, SOO-JUNG CHOI