Patents by Inventor Weon-Ki Yoon

Weon-Ki Yoon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8345801
    Abstract: A system and method for signal mismatch compensation in a wireless receiver is disclosed. The method includes receiving an in-phase (I) signal and a quadrature (Q) signal corresponding to the I signal, the Q signal having an ideal phase offset of 90 degrees from the I signal, where there is a phase and gain mismatch between the I signal and Q signal. The method adjusts the phase offset between the I signal and the Q signal to minimize the IQ power, where the IQ power is the average-time power of a digital baseband in-phase (DB-I) signal and a digital baseband quadrature (DB-Q) signal, corresponding to the I signal and Q signal, respectively. The method adjusts the gain of the Q signal to minimize the IQ power, whereby the phase and gain mismatch between the I signal and Q signal is minimized.
    Type: Grant
    Filed: November 10, 2005
    Date of Patent: January 1, 2013
    Inventor: Weon-Ki Yoon
  • Patent number: 7792228
    Abstract: A multi-mode digital down-converter for down-converting an incoming IF signal to baseband according to a selected air interface standard. The down-converter comprises a re-configurable gain control block controlled by a first gain parameter for amplifying the incoming IF signal and a mixer stage for down-converting the amplified incoming IF signal to produce a first in-phase baseband signal. The down-converter further comprises a reconfigurable CIC decimation filter block controlled by a second gain parameter and a first decimation parameter. The reconfigurable CIC decimation filter block filters the first in-phase baseband signal according to the second gain parameter and decimates the first in-phase baseband signal according to the first decimation parameter. The first and second gain parameters and the first decimation parameter are determined by the selected air interface standard.
    Type: Grant
    Filed: February 11, 2005
    Date of Patent: September 7, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Weon-Ki Yoon
  • Publication number: 20100029324
    Abstract: An architecture for a receiver component in a wireless communications system is disclosed—one that supports both zero intermediate frequency (ZIF) and near-zero intermediate frequency (NZIF) operation. The architecture provides a down-conversion segment, and a local oscillator segment operatively associated with the down-conversion segment. An analog-to-digital conversion (ADC) segment is adapted to receive signals from the down-conversion segment and introduce the signals into a digital intermediate frequency (DIF) construct. The DIF construct performs a DC offset compensation or DC residue filtering on NZIF-based signals, and droop or mismatch compensation. Image removal is performed on NZIF-based signals, and DC offset compensation is performed on ZIF-based signals. Compensated signals are amplified to some nominal or desired level, and interpolation filtering of the amplified signals is performed prior to transmission thereof.
    Type: Application
    Filed: July 6, 2009
    Publication date: February 4, 2010
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Michael L. Brobston, Steven Loh, Seong Eun Kim, Weon Ki Yoon
  • Patent number: 7558550
    Abstract: An architecture for a receiver component in a wireless communications system is disclosed—one that supports both zero intermediate frequency (ZIF) and near-zero intermediate frequency (NZIF) operation. The architecture provides a down-conversion segment, and a local oscillator segment operatively associated with the down-conversion segment. An analog-to-digital conversion (ADC) segment is adapted to receive signals from the down-conversion segment and introduce the signals into a digital intermediate frequency (DIF) construct. The DIF construct performs a DC offset compensation or DC residue filtering on NZIF-based signals, and droop or mismatch compensation. Image removal is performed on NZIF-based signals, and DC offset compensation is performed on ZIF-based signals. Compensated signals are amplified to some nominal or desired level, and interpolation filtering of the amplified signals is performed prior to transmission thereof.
    Type: Grant
    Filed: January 5, 2006
    Date of Patent: July 7, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Michael L. Brobston, Steven Loh, Seong Eun Kim, Weon Ki Yoon
  • Patent number: 7369873
    Abstract: A multi-mode mobile station comprising 1) reconfigurable transceiver circuitry for communicating with wireless networks operating under different air interface standards; 2) a memory for storing at least a download configuration file and a home configuration file; and 3) a main controller for configuring the reconfigurable transceiver circuitry to operate according to a home network wireless standard using home configuration data retrieved from the home configuration file. If the main controller determines that a network operating according to the home network wireless standard cannot be found, the main controller is further capable of configuring the reconfigurable transceiver circuitry to operate according to a download channel wireless standard using download configuration data retrieved from the download configuration file.
    Type: Grant
    Filed: February 10, 2005
    Date of Patent: May 6, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Michael L. Brobston, Weon-Ki Yoon, William M. Hurley
  • Publication number: 20070104291
    Abstract: A system and method for signal mismatch compensation in a wireless receiver is disclosed. The method includes receiving an in-phase (I) signal and a quadrature (Q) signal corresponding to the I signal, the Q signal having an ideal phase offset of 90 degrees from the I signal, where there is a phase and gain mismatch between the I signal and Q signal. The method adjusts the phase offset between the I signal and the Q signal to minimize the IQ power, where the IQ power is the average-time power of a digital baseband in-phase (DB-I) signal and a digital baseband quadrature (DB-Q) signal, corresponding to the I signal and Q signal, respectively. The method adjusts the gain of the Q signal to minimize the IQ power, whereby the phase and gain mismatch between the I signal and Q signal is minimized.
    Type: Application
    Filed: November 10, 2005
    Publication date: May 10, 2007
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Weon-Ki Yoon
  • Patent number: 7031409
    Abstract: A digital automatic gain control (AGC) circuit for use in a radio frequency (RF) receiver. The AGC circuit comprises: 1) a first shifter for receiving an in-phase signal as a first series of X-bit samples and left-shifting each X-bit sample by a number of bits determined by a coarse scaling factor; 2) a first limiter for receiving the D most significant bits of the output of the first shifter and outputting a subset of the D most significant bits of the first shifter output; 3) a first multiplier for multiplying the subset of the D most significant bits of the first shifter output by a fine scaling factor to produce a first M-bit product; and 4) a gain adjustment circuit for comparing a power signal derived from the first M-bit product to a maximum threshold value and generating the coarse scaling factor and the fine scaling factor.
    Type: Grant
    Filed: August 23, 2002
    Date of Patent: April 18, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Michael L. Brobston, Jason Rock, Weon-Ki Yoon, Min Jeon
  • Publication number: 20060023811
    Abstract: A digital in-phase/quadrature (I/Q) demodulator for use in RF receivers, wireless base stations, wireless mobile stations and other components of wireless networks. The digital I/Q demodulator extracts and resolves I and Q components of a demodulated digital data signal from a modulated digital data signal input thereto. The digital I/Q demodulator includes a self contained carrier signal recovery loop for constructing, from acquired phase information and a frequency input the digital I/Q demodulator from a first of plural programmable inputs thereto, a local carrier signal used in the demodulation process.
    Type: Application
    Filed: July 29, 2004
    Publication date: February 2, 2006
    Inventor: Weon-Ki Yoon
  • Publication number: 20050201494
    Abstract: A multi-mode digital down-converter for down-converting an incoming IF signal to baseband according to a selected air interface standard. The down-converter comprises a re-configurable gain control block controlled by a first gain parameter for amplifying the incoming IF signal and a mixer stage for down-converting the amplified incoming IF signal to produce a first in-phase baseband signal. The down-converter further comprises a reconfigurable CIC decimation filter block controlled by a second gain parameter and a first decimation parameter. The reconfigurable CIC decimation filter block filters the first in-phase baseband signal according to the second gain parameter and decimates the first in-phase baseband signal according to the first decimation parameter. The first and second gain parameters and the first decimation parameter are determined by the selected air interface standard.
    Type: Application
    Filed: February 10, 2005
    Publication date: September 15, 2005
    Applicant: SAMSUNG ELECTRONICS Co., LTD.
    Inventor: Weon-Ki Yoon
  • Publication number: 20050201501
    Abstract: A multi-mode digital down-converter for down-converting an incoming IF signal to baseband according to a selected air interface standard. The down-converter comprises a re-configurable gain control block controlled by a first gain parameter for amplifying the incoming IF signal and a mixer stage for down-converting the amplified incoming IF signal to produce a first in-phase baseband signal. The down-converter further comprises a reconfigurable CIC decimation filter block controlled by a second gain parameter and a first decimation parameter. The reconfigurable CIC decimation filter block filters the first in-phase baseband signal according to the second gain parameter and decimates the first in-phase baseband signal according to the first decimation parameter. The first and second gain parameters and the first decimation parameter are determined by the selected air interface standard.
    Type: Application
    Filed: February 11, 2005
    Publication date: September 15, 2005
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Weon-Ki Yoon
  • Publication number: 20050202841
    Abstract: A multi-mode mobile station comprising 1) reconfigurable transceiver circuitry for communicating with wireless networks operating under different air interface standards; 2) a memory for storing at least a download configuration file and a home configuration file; and 3) a main controller for configuring the reconfigurable transceiver circuitry to operate according to a home network wireless standard using home configuration data retrieved from the home configuration file. If the main controller determines that a network operating according to the home network wireless standard cannot be found, the main controller is further capable of configuring the reconfigurable transceiver circuitry to operate according to a download channel wireless standard using download configuration data retrieved from the download configuration file.
    Type: Application
    Filed: February 10, 2005
    Publication date: September 15, 2005
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Michael Brobston, Weon-Ki Yoon, William Hurley
  • Publication number: 20040037377
    Abstract: A digital automatic gain control (AGC) circuit for use in a radio frequency (RF) receiver. The AGC circuit comprises: 1) a first shifter for receiving an in-phase signal as a first series of X-bit samples and left-shifting each X-bit sample by a number of bits determined by a coarse scaling factor; 2) a first limiter for receiving the D most significant bits of the output of the first shifter and outputting a subset of the D most significant bits of the first shifter output; 3) a first multiplier for multiplying the subset of the D most significant bits of the first shifter output by a fine scaling factor to produce a first M-bit product; and 4) a gain adjustment circuit for comparing a power signal derived from the first M-bit product to a maximum threshold value and generating the coarse scaling factor and the fine scaling factor.
    Type: Application
    Filed: August 23, 2002
    Publication date: February 26, 2004
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Michael L. Brobston, Jason Rock, Weon-Ki Yoon, Min Jeon