Patents by Inventor Wern Ming Koe

Wern Ming Koe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240136372
    Abstract: A pixel for an ambient light and/or color sensor includes a plurality of pinned photodiodes. The pixel also includes a floating diffusion region. A ratio of an active area of the plurality of pinned photodiodes to an area of the floating diffusion region is greater than 150.
    Type: Application
    Filed: February 22, 2022
    Publication date: April 25, 2024
    Inventors: Benjamin Joseph SHEAHAN, Jong Mun PARK, Robert VAN ZEELAND, Kirk David PETERSON, Wern Ming KOE, George Richard KELLY, Mario MANNINGER, Dong-Long LIN, Pascale FRANCIS, Koen RUYTHOOREN
  • Patent number: 10236768
    Abstract: The present disclosure relates to a structure which includes a diode-based Dickson charge pump which is configured to use an independent multi-gate device to reduce a threshold voltage of a plurality of transistor diodes during a charging and pumping phase.
    Type: Grant
    Filed: May 19, 2017
    Date of Patent: March 19, 2019
    Assignee: GLOBALFOUNDARIES INC.
    Inventor: Wern Ming Koe
  • Publication number: 20180337596
    Abstract: The present disclosure relates to a structure which includes a diode-based Dickson charge pump which is configured to use an independent multi-gate device to reduce a threshold voltage of a plurality of transistor diodes during a charging and pumping phase.
    Type: Application
    Filed: May 19, 2017
    Publication date: November 22, 2018
    Inventor: Wern Ming KOE
  • Patent number: 10109620
    Abstract: Switched-capacitor charge pump implemented in FDSOI process technology and a method of forming them are provided. Embodiments include providing a FDSOI substrate; providing a plurality of stages of a first and a second pair of an NFET and PFET over the FDSOI substrate coupled between an input terminal and an output terminal, the first and second pair of each stage being opposite each other; providing a plurality of a first and a second capacitor over the FDSOI substrate, each first and second capacitor connected to a first and a second pair of NFET and PFET of a stage, respectively; connecting a back-gate of a NFET and a back-gate of a PFET of each pair; connecting the connected NFET and PFET back-gates to a front-gate of the pair; and connecting a source of each pair to a front gate of an opposite pair within the stage.
    Type: Grant
    Filed: July 26, 2017
    Date of Patent: October 23, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventor: Wern Ming Koe
  • Publication number: 20100073207
    Abstract: Delta-sigma analog-to-digital converters (ADCs) and methods to calibrate methods to delta-sigma ADCs are disclosed. In one particular example, a delta-sigma ADC is described, including an n-bit feedback digital-to-analog converter (DAC) having a number of unit elements, and is configured to provide a feedback signal to a summing device, which generates a difference signal based on an analog input signal and the feedback signal. An n-bit ADC is included to generate an n-bit digital signal based on the difference signal. A dynamic element matching device selects one or more unit elements in the DAC based on the n-bit digital signal. A storage device, such as a memory, stores error coefficients corresponding to the plurality of unit elements. Finally, a digital corrector is included to receive the selection of unit elements, receive error coefficients corresponding to the selected unit elements, and adjust the n-bit digital signal based on the received error coefficients.
    Type: Application
    Filed: September 22, 2008
    Publication date: March 25, 2010
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Amit Kumar Gupta, Karthikeyan Soundarapandian, Yong-In Park, Wern Ming Koe
  • Patent number: 7312738
    Abstract: A sigma delta signal treating apparatus includes: (a) a low pass filtered signal path including at least one low pass filter; and (b) a quantization noise filtered signal path coupled with the low pass filtered signal path; the quantization noise filtered signal path including at least one high pass filter and at least one feedback notch filter.
    Type: Grant
    Filed: October 27, 2005
    Date of Patent: December 25, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Wern Ming Koe, Yong-In Park