Abstract: In order to provide a network element for switching time-division multiplex signals in a transport network, which allows higher capacity at moderate equipment costs, the network element has a number of input ports (I; IO1-IO8), a number of output ports (O; IO1-IO8) and a switch fabric ( ) SF; 58) interconnecting the input and output ports (IO1-IO8). The switching fabric ( ) SF; 58) is a cell based switch comprising one or more switch modules ( ) SE1-SEn) which are adapted to switch fixed-length cells on the basis of addresses contained in cell headers of the cells. The input ports (I) contain a segmentation device (11) for segmenting an input time-division multiplex signal into fixed-length cells and assigning address information to each cell. The output ports (O) contain a reassembly device (14) for reassembling cells received from said switch fabric (SF; 58) into an output time-division multiplex signal. The address information contains a fabric address (H1, H2) and a TDM address (P0, P1).

Abstract: A network element for a transport network contains a multistage lower order switching matrix with at least an input matrix stage and an output matrix stage designed to switch lower order multiplex units and with a center stage capable of switching higher order multiplex units, only, thereby connecting the input and output stages.

Abstract: In order to provide a network element for switching time-division multiplex signals in a transport network, which allows higher capacity at moderate equipment costs, the network element has a number of input ports (I; IO1-IO8), a number of output ports (O; IO1-IO8) and a switch fabric ( ) SF; 58) interconnecting the input and output ports (IO1-IO8). The switching fabric ( ) SF; 58) is a cell based switch comprising one or more switch modules ( ) SE1-SEn) which are adapted to switch fixed-length cells on the basis of addresses contained in cell headers of the cells. The input ports (I) contain a segmentation device (11) for segmenting an input time-division multiplex signal into fixed-length cells and assigning address information to each cell. The output ports (O) contain a reassembly device (14) for reassembling cells received from said switch fabric (SF; 58) into an output time-division multiplex signal. The address information contains a fabric address (H1, H2) and a TDM address (P0, P1).

Abstract: A network element with equipment protection has first and second redundant signal paths for first and second redundant signals; a selector for selecting either of the two redundant signals as active; and first and second transition monitors coupled to the first and second signal paths, respectively, for monitoring the first and second signals for bit level transitions. The selector is controlled by the transition monitors to alter selection in the case that the selected signal does not contain bit level transitions while the non-selected signal does.

Abstract: A network device (NWE) for a digital transmission network with synchronous digital hierarchy receives data steams containing frames with data packets mapped therein and addressed by a phase reference identifier. Internally, the network device has redundant transfer paths which potentially cause different delay. The network element compensates for that delay by adjusting the phase reference identifier allocated to a respective data packet by a predetermined phase correcting value, leading in the phase, which corresponds to a maximum expected delay for transfer of the data packets on internal transfer paths, and by buffering the data packet by a buffering time such that its buffering time and its delay actually needed for passing through the network device in total correspond to the maximum expected delay taken into account by the phase adjustment.

Abstract: A network element for a transport network contains a multistage lower order switching matrix with at least an input matrix stage and an output matrix stage designed to switch lower order multiplex units and with a center stage capable of switching higher order multiplex units, only, thereby connecting the input and output stages.

Abstract: A network element with equipment protection has first and second redundant signal paths for first and second redundant signals; a selector for selecting either of the two redundant signals as active; and first and second transition monitors coupled to the first and second signal paths, respectively, for monitoring the first and second signals for bit level transitions. The selector is controlled by the transition monitors to alter selection in the case that the selected signal does not contain bit level transitions while the non-selected signal does.

Abstract: A method of synchronizing at least one receiver module (MOD 1, MOD2), in particular a receiver module in a telecommunications network or in a network device of a telecommunications network, has the following steps: A first clock signal (TS 1) and a second clock signal (TS2) are sent to the at least one receiver module (MOD 1, MOD2). In addition, at least one item of master-slave-status information (MSX) about the at least one first clock signal (TS1) and/or the second clock signal (TS2) is sent to the at least one receiver module (MOD1, MOD2). Based on the item of master-slave-status information (MSX), the at least one receiver module (MOD 1, MOD2) selects the first clock signal (TS 1) or the second clock signal (TS2) as master synchronization signal for its synchronization.

Abstract: The present invention relates to a digital communication device comprising interconnected modules for processing and/or handling received data signals, wherein said interconnected modules each comprise means for monitoring (monitoring means) said data signal and for generating an output data signal having a predetermined signal status (squelched data signal) if said data signal is erroneous. The invention also relates to a method for processing a data signal within a communication device, preferably a communication device according to the present invention.

Abstract: Automatic control of parameters of optical components such as colored losers in a transmit side WDM system includes the following steps. At a receiver side (NE21-NE2n)) predefined characteristics of a received signal are measured. The results (MEAS) of these measurements are communicated to a remote control system (NMS1) which runs an algorithm to determine corrective adjustment parameters (ADJ) and communicates them to the transmitter side (NE11-NE1n), which adjusts the optical components accordingly. The adjustment algorithm is implemented in one of the affected network elements or in the related network management system, preferably in the element manager (NMS1) of the affected network elements. The measurements are provided automatically to the algorithm; the related adjustments are provided automatically to the network elements, which contain the transmitters to be adjusted.

Abstract: A synchronous transmission system is disclosed in which the transmission paths (leased lines) extend over several individual transmission systems (Sx). Monitoring devices (NIM) with access to at least one byte of the control data area are provided in synchronous transmission systems to write data into or read data out of the control data area. The monitoring devices (NIM) may thus be controlled and monitored by a signal source (S1).

Abstract: A method of synchronising at least one receiver module (MOD1, MOD2), in particular a receiver module in a telecommunications network or in a network device of a telecommunications network, has the following steps: A first clock signal (TS1) and a second clock signal (TS2) are sent to the at least one receiver module (MOD1, MOD2). In addition, at least one item of master-slave-status information (MSX) about the at least one first clock signal (TS1) and/or the second clock signal (TS2) is sent to the at least one receiver module (MOD1, MOD2). Based on the item of master-slave-status information (MSX), the at least one receiver module (MOD1, MOD2) selects the first clock signal (TS1) or the second clock signal (TS2) as master synchronisation signal for its synchronisation.

Abstract: An optical cross-connect (OCX), which is designed for the switching of so-called Optical Channels of different multiplex levels with respectively defined bit rates, has a number of input/output ports (I/O) which are respectively adapted to transmit and receive communication signals of a particular multiplex level, and a switching matrix (S) which is connected to the input/output ports (I/O). The switching matrix (S) is a space switching matrix which is transparent for communication signals of all multiplex levels. In order to provide the interface between the individual multiplex levels, the cross-connect (OCX) has at least one multiplexer (MUX), which is also connected to the switching matrix (S).

Abstract: A compensation module or for a network device of a telecommunications network delays a first clock signal by a predetermined first delay time to form a delayed first clock signal and delays a second clock signal by a predetermined second delay time to form a delayed second clock signal. The compensation module then adapts the second delay time so that the delayed second clock signal is adapted to the phase of the delayed first clock signal.

Abstract: A network device (NWE) for a digital transmission network with synchronous digital hierarchy receives data steams containing frames with data packets mapped therein and addressed by a phase reference identifier. Internally, the network device has redundant transfer paths which potentially cause different delay. The network element compensates for that delay by adjusting the phase reference identifier allocated to a respective data packet by a predetermined phase correcting value, leading in the phase, which corresponds to a maximum expected delay for transfer of the data packets on internal transfer paths, and by buffering the data packet by a buffering time such that its buffering time and its delay actually needed for passing through the network device in total correspond to the maximum expected delay taken into account by the phase adjustment.

Abstract: An optical cross-connect (OCX), which is designed for the switching of so-called Optical Channels of different multiplex levels with respectively defined bit rates, has a number of input/output ports (IO1, IO2, IO3) which are respectively adapted to transmit and receive communication signals of a particular multiplex level. The cross-connect furthermore has a space switching matrix (S) which is adapted to switch communication signals of the lowest multiplex level.

Abstract: An optical cross-connect (OCX), which is designed for switching so-called optical channels of different multiplex levels with respectively defined bit rates, comprises a number of input/output ports (IO1, IO2, IO3) which are respectively adapted for transmitting and receiving communication signals of a given multiplex level. The cross-connect further comprises, for each multiplex level, a separate space switching matrix (S1, S2, S3) which is adapted to that multiplex level. The individual switching matrices (S1, S2, S3) are interconnected via multiplexers (MUX1, MUX2).

Abstract: The invention concerns a network element and an input-output unit (1) for a synchronous transmission system according to the standard for Synchronous Digital Hierarchy or according to the comparable Synchronous Optical Network (SONET) standard. The input-output unit (1) contains a signal processing device (2) that has a reception data memory (5), a transmission data memory (7), a control unit (6) and a processor (3). The processor (3) is a digital signal processor which essentially carries out the processing of a STM-N signal.

Abstract: In a data transmission system, a switching network in a connection node (VK) includes switch groups (SCH) for switching channels, which are each assigned to one or more time slots within the framework of a multiplex time signal, e.g. virtual containers of a STM-1 frame according to CCITT recommendations G707 to G.709. Each switch group (SCH) is modular and linked to one another, and contains a memory (DS) with several independently readable memory outputs (SA1 to SA4), through which the storage area can be accessed. Each part signal of a respective memory address can be connected with a data output of the switch group (SCH) through selectors (SEL1 to SEL4). A connecting memory (VB1 to VB4) controls the reading of each part signal from the memory (DS) to a memory output (SA1 to SA4) and a selector (SEL1 to SEL4). A coupling field may be composed of switch groups (SCH) arranged in columns and lines, as required.

Abstract: The network access node of a digital communication system for the bidirectional transmission of message signals between, for example, a switching center and subscribers as an electrically switchable connection between the lines to the switching centers with a first interface and the lines to the subscribers with a second interface. The first interface is preferably an interface for a time-division multiplex signal with a transmission rate of 2 Mbit/s; the second interface is preferably an interface for signals in multiple access with time-division multiplex (TDM/TDMA). The buffer memory of the TDM/TDMA system is made up of partial memories arranged as a matrix. The partial memories are used simultaneously as a buffer memory for the circuit of the paths.