Abstract: An integrated circuit can be switched between operating modes without the need for a dedicated mode selection pin. A circuit for operation at a specified maximum supply voltage comprises first and second supply terminals, a first signal input for application of a regular input signal, a second signal input, and an output. The circuit further comprises a multiplexer with first and second inputs connected to the first and second signal inputs, respectively, for selectively switching either of the first and second signal inputs to the output under control of a selection signal. A gate circuit provides the selection signal to the multiplexer. The input of the gate circuit is driven by control circuitry. Clamping circuitry is provided that limits the voltage at the first input of the multiplexer. With such a circuit design, a relatively high voltage applied to the first signal input will switch the circuit to another operating mode, such as a test mode.

Abstract: An integrated circuit can be switched between operating modes without the need for a dedicated mode selection pin. A circuit for operation at a specified maximum supply voltage comprises first and second supply terminals, a first signal input for application of a regular input signal, a second signal input, and an output. The circuit further comprises a multiplexer with first and second inputs connected to the first and second signal inputs, respectively, for selectively switching either of the first and second signal inputs to the output under control of a selection signal. A gate circuit provides the selection signal to the multiplexer. The input of the gate circuit is driven by control circuitry. Clamping circuitry is provided that limits the voltage at the first input of the multiplexer. The control circuitry detects a voltage at the first signal input that exceeds the specified maximum supply voltage by a given amount and, in response, applies a drive signal to the input of the gate circuit.

Abstract: The present invention relates to a circuit arrangement integrated in a semiconductor circuit. In modern microprocessor systems with high clock rates (50 MHz and more) special chips with narrow tolerance ranges as regards their switching speed are required. The circuit arrangement according to the invention compensates the switching speed fluctuations due to temperature fluctuations and process spread by generating an internal operating voltage and controlling said voltage in such a manner that it counteracts the fluctuations of the switching speed due to temperature changes and process spread and compensates said fluctuations.

Abstract: A bus driver circuit for applying a binary signal to a bus line comprises an input transistor (Q.sub.1) for receiving the signal to be applied to the bus line and an output transistor (Q.sub.2) which taps the signal from the emitter of the input transistor and furnishes its output signal at its collector via a Schottky diode (D.sub.1). Between the base and the collector of the output transistor (Q.sub.2) the collector-emitter path of a transistor (Q.sub.3) is inserted, to the base of which a reference voltage (U.sub.ref) for defining the low value (L) of the binary signal to be applied to the bus line is applied via a Schottky diode (D.sub.3).

Abstract: An integrated circuit is described which includes a plurality of output transistors (T1, T2, . . . Tn) for emitting binary signals to associated output terminals (A1, A2, . . . An). The integrated circuit further includes at least one ground terminal (M; M1, M2 . . . Mn). Between the base of each transistor (T1, T2, . . . Tn) and the at least one ground terminal (M; M1, M2, . . . Mn) a current source (R1, D1) controlled by the base voltage is inserted.

Abstract: An electrically programmable logic array (10) for binary signals having signal inputs A.sub.0 -A.sub.x) and signal outputs Q.sub.0 -Q.sub.i) comprises two row lines (a.sub.0,a.sub.0' -a.sub.x, a.sub.x') for each signal input. The signal applied to the signal input is generatable at the one row line in non-negated form and at the other row line in negated form. For each signal output a column line (q.sub.0 -q.sub.i) is provided.In the non-programmable state between each row line and each column line there is an electrically conductive connection interruptable for the purpose of programming. Inserted into the connection between the signal inputs and each associated row line is a controllable switching member (S.sub.0,S.sub.0',-S.sub.x, S.sub.x') which is controllable by a control signal applied thereto in such a manner that its output signal changes with the signal applied to the associated signal input or irrespective of said signal always retains a predetermined signal value.

Abstract: A programmable circuit arrangement is described which can be programmed by applying a programming voltage so that it delivers at its output a signal having a predetermined binary value. The circuit arrangement comprises an input means responsive to the programming voltage. Further, it comprises a conducting means connected to the input means and capable of being brought to a non-conductive state upon application of the programming voltage to the input means. The circuit arrangement further comprises an output means connected to the conductive means and delivering a signal having one binary value in the conductive state of the conductive means and the other binary value in the non-conductive state of the conductive means.