Patents by Inventor Werner Ertle

Werner Ertle has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SEMICONDUCTOR WAFER WITH ELECTRICALLY CONNECTED CONTACT AND TEST AREAS
    Publication number: 20110294238
    Abstract: The invention relates to an arrangement of contact areas and test areas on patterned semiconductor chips. The contact areas and the test areas are electrically connected to one another via a conduction web. Whereas the contact areas are arranged in a first region, which has no components of an integrated circuit, the test areas lie in a second region of the top side of the semiconductor chip, which region has components of an integrated circuit.
    Type: Application
    Filed: July 28, 2011
    Publication date: December 1, 2011
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Werner Ertle, Bernd Goller, Michael Horn, Bernd Kothe
  • Semiconductor wafer with electrically connected contact and test areas
    Patent number: 8044394
    Abstract: The invention relates to an arrangement of contact areas and test areas on patterned semiconductor chips. The contact areas and the test areas are electrically connected to one another via a conduction web. Whereas the contact areas are arranged in a first region, which has no components of an integrated circuit, the test areas lie in a second region of the top side of the semiconductor chip, which region has components of an integrated circuit.
    Type: Grant
    Filed: July 29, 2003
    Date of Patent: October 25, 2011
    Assignee: Infineon Technologies AG
    Inventors: Werner Ertle, Bernd Goller, Michael Horn, Bernd Kothe
  • Semiconductor structure integrated under a pad
    Patent number: 7190077
    Abstract: An integrated semiconductor structure has a substrate, a semiconductor element located on the substrate, a pad metal, metal layers located between the pad metal and the substrate, and insulation layers that separate the metal layers from one another. The pad metal extends over at least—part of the semiconductor element. Below the surface of the pad metal, at least the top two metal layers include two or more adjacent interconnects.
    Type: Grant
    Filed: June 12, 2003
    Date of Patent: March 13, 2007
    Assignee: Infineon Technologies AG
    Inventors: Robert Bauer, Werner Ertle, Till Frohnmüller, Bernd Goller, Reinhard Greiderer, Oliver Nagler, Olaf Schmeckebier, Wolfgang Stadler
  • Semiconductor wafer with electrically connected contact and test areas
    Publication number: 20060097386
    Abstract: The invention relates to an arrangement of contact areas and test areas on patterned semiconductor chips. The contact areas and the test areas are electrically connected to one another via a conduction web. Whereas the contact areas are arranged in a first region, which has no components of an integrated circuit, the test areas lie in a second region of the top side of the semiconductor chip, which region has components of an integrated circuit.
    Type: Application
    Filed: July 29, 2003
    Publication date: May 11, 2006
    Inventors: Werner Ertle, Bernd Goller, Michael Horn, Bernd Kothe
  • Method for producing a semiconductor circuit, and corresponding semiconductor circuit
    Publication number: 20050285199
    Abstract: A semiconductor circuit containing a pad for electrical bonding of the semiconductor circuit and a metal arrangement disposed beneath the pad. The metal arrangement is in a metal layer of the semiconductor circuit located closest to the pad and is electrically insulated from the pad and from a strip conductor located beneath the metal arrangement. More than one metal layer can contain a metal arrangement. Each metal arrangement is a full-area plate that overlaps all edges of the pad or has a regular structure of small square plates. If adjacent metal arrangements are constructed from small plates, the plates in one metal arrangement overlap to cover gaps in the other metal arrangement.
    Type: Application
    Filed: May 25, 2005
    Publication date: December 29, 2005
    Inventors: Wolfgang Stadler, Werner Ertle, Bernd Goller, Michael Horn, Manfred Hermann, Giuseppe Miccoli
  • Semiconductor structure integrated under a pad
    Publication number: 20050242374
    Abstract: An integrated semiconductor structure has a substrate, a semiconductor element located on the substrate, a pad metal, metal layers located between the pad metal and the substrate, and insulation layers that separate the metal layers from one another. The pad metal extends over at least -part of the semiconductor element. Below the surface of the pad metal, at least the top two metal layers include two or more adjacent interconnects.
    Type: Application
    Filed: June 12, 2003
    Publication date: November 3, 2005
    Inventors: Robert Bauer, Werner Ertle, Till Frohnmuller, Bernd Goller, Reinhard Greiderer, Oliver Nagler, Olaf Schmeckebier, Wolfgang Stadler