Abstract: An energy storage device having: a high-temperature regenerator containing a solid, particularly porous storage material (S); a working gas (A) as the heat transfer medium to transfer heat between the storage material (S) and the working gas (A) flowing through; and a charging circuit and a discharging circuit for the working gas (A). The charging circuit is designed such that starting from a pre-heating unit at least one first heat transfer duct of a recuperator, a first compressor (HO), the high-temperature regenerator, a second heat transfer duct of the recuperator and then a first expander are interconnected, thus forming a circuit, so as to conduct fluid.

Abstract: An energy storage device having: a high-temperature regenerator containing a solid, particularly porous storage material (S); a working gas (A) as the heat transfer medium to transfer heat between the storage material (S) and the working gas (A) flowing through; and a charging circuit and a discharging circuit for the working gas (A). The charging circuit is designed such that starting from a pre-heating unit at least one first heat transfer duct of a recuperator, a first compressor (HO), the high-temperature regenerator, a second heat transfer duct of the recuperator and then a first expander are interconnected, thus forming a circuit, so as to conduct fluid.

Abstract: An energy storage device for storing energy including: a high-temperature regenerator containing a storage material and a working gas as heat transfer medium for the purpose of exchanging heat between the storage material and the traversing working gas, a closed charging circuit for the working gas, including a first compressor, a first expander, a first recuperator having a first and a second heat exchange duct, the high-temperature regenerator and a pre-heater, wherein the first compressor is coupled to the first expander by a shaft, a discharging circuit for the working gas, and including a switch that selectively connects the high-temperature regenerator to either the charging circuit or the discharging circuit, such that the circuit containing the high-temperature regenerator forms a closed circuit.

Abstract: An energy storage device for storing energy including: a high-temperature regenerator containing a storage material and a working gas as heat transfer medium for the purpose of exchanging heat between the storage material and the traversing working gas, a closed charging circuit for the working gas, including a first compressor, a first expander, a first recuperator having a first and a second heat exchange duct, the high-temperature regenerator and a pre-heater, wherein the first compressor is coupled to the first expander by a shaft, a discharging circuit for the working gas, and including a switch that selectively connects the high-temperature regenerator to either the charging circuit or the discharging circuit, such that the circuit containing the high-temperature regenerator forms a closed circuit.

Abstract: When forming metallization layers of advanced semiconductor devices, one often has to fill apertures with a high aspect ratio with a metal, such as copper. The present disclosure provides a convenient method for forming apertures with a high aspect ratio in an insulating layer. This insulating layer may have been deposited on the surface of a semiconductor device. The proposed method relies on an ion implantation step performed on the insulating layer, followed by an etch, which is preferably a wet etch.

Abstract: When forming metallization layers of advanced semiconductor devices, one often has to fill apertures with a high aspect ratio with a metal, such as copper. The present disclosure provides a convenient method for forming apertures with a high aspect ratio in an insulating layer. This insulating layer may have been deposited on the surface of a semiconductor device. The proposed method relies on an ion implantation step performed on the insulating layer, followed by an etch, which is preferably a wet etch.

Abstract: One embodiment relates to an integrated circuit formed on a semiconductor body having interconnect between source/drain regions of a first and second transistor. The interconnect includes a metal body arranged underneath the surface of the semiconductor body. A contact element establishes electrical contact between the metal body and the source/drain regions of the first and second transistor. The contact element extends along a connecting path between the source/drain regions of the first and second transistors. Other methods, devices, and systems are also disclosed.

Abstract: An integrated circuit includes a contact structure with a buried first and a protruding second portion. The buried first portion is arranged in a cavity formed in a semiconductor structure and is in direct contact with the semiconductor structure. The protruding second portion is arranged above the main surface of the semiconductor structure and in direct contact with a conductive structure that is spaced apart from or separated from the main surface of the semiconductor structure. An insulator structure is arranged below and in direct contact with the contact structure.

Abstract: In one embodiment, a memory cell includes a bit line arranged in a semiconductor substrate and a bit line contact region arranged adjacent the bit line. A word line is arranged above the bit line contact region in a trench formed in the semiconductor substrate. A generally U-shaped insulating layer is arranged in a bottom region of the trench and separates the bit line and the bit line contact region from the word line.

Abstract: One embodiment relates to an integrated circuit formed on a semiconductor body having interconnect between source/drain regions of a first and second transistor. The interconnect includes a metal body arranged underneath the surface of the semiconductor body. A contact element establishes electrical contact between the metal body and the source/drain regions of the first and second transistor. The contact element extends along a connecting path between the source/drain regions of the first and second transistors. Other methods, devices, and systems are also disclosed.

Abstract: An integrated circuit includes a contact structure with a buried first and a protruding second portion. The buried first portion is arranged in a cavity formed in a semiconductor structure and is in direct contact with the semiconductor structure. The protruding second portion is arranged above the main surface of the semiconductor structure and in direct contact with a conductive structure that is spaced apart from or separated from the main surface of the semiconductor structure. An insulator structure is arranged below and in direct contact with the contact structure.

Abstract: A tip (8) comprising a first portion (8r) that is configured to be removably coupled to a laser porator (10) and a second portion (8h) defining an aperture (8x) and comprising a tissue biasing element (8a) that is configured to deform at least a portion (1a) of a tissue (1) that is subject to a laser treatment.

Abstract: In one embodiment, a memory cell includes a bit line arranged in a semiconductor substrate and a bit line contact region arranged adjacent the bit line. A word line is arranged above the bit line contact region in a trench formed in the semiconductor substrate. A generally U-shaped insulating layer is arranged in a bottom region of the trench and separates the bit line and the bit line contact region from the word line.

Abstract: An integrated circuit having an active semiconductor device is formed comprising a trench defined by conductor lines previously formed.

Abstract: The present invention provides a manufacturing method for an integrated semiconductor structure comprising the steps of: providing a semiconductor substrate with a main surface; forming a wiring metal layer above said main surface; forming a doped getter layer on said wiring metal layer; and forming at least one additional wiring metal layer on said doped getter layer. The present invention also provides a corresponding integrated semiconductor structure and a semiconductor memory device.

Abstract: The present invention provides a manufacturing method for an integrated semiconductor structure comprising the steps of: providing a semiconductor substrate having a plurality of gate stacks in a first region and at least one gate stack in a second region; forming a sacrificial plug made of a first material surrounded by an isolation layer between two adjacent gate stacks in the first region; depositing a planarisation layer over said plurality of gate stacks in said first region and said at least one gate stack in said second region; backpolishing said planarisation layer such that the upper surface of said sacrificial plug is exposed; forming a structured hardmask layer made of said first material on said backpolished planarisation layer which structured hardmask layer adjoins said sacrificial plug and has at least one opening in said second region; forming at least one contact hole in said second region under said at least one opening in said second region, said at least one contact hole exposing a substra

Abstract: In a method for producing a semiconductor structure a semiconductor a substrate with a top surface is provided. A gate dielectric layer is provided on the top surface and on the gate dielectric layer is provided a memory cell array region with a first plurality of gate stacks and a peripheral element region with a second plurality of gate stacks. A dielectric layer is provided over the memory cell array region and the peripheral element region. A first source/drain implantation over the memory cell array region and the peripheral element region is carried out, a blocking mask over the memory cell array region is formed, the dielectric layer is removed using the blocking mask, and a second source/drain implantation over the memory cell array region and the peripheral element region is carried out, wherein the memory cell array region is protected by a mask.

Abstract: The present invention provides a manufacturing method for an integrated semiconductor structure comprising the steps of: providing a semiconductor substrate having a plurality of gate stacks in a first region and at least one gate stack in a second region; forming a sacrificial plug made of a first material surrounded by an isolation layer between two adjacent gate stacks in the first region; depositing a polarization layer over said plurality of gate stacks in said first region and said at least one gate stack in said second region; backpolishing said polarization layer such that the upper surface of said sacrificial plug is exposed; forming a structured hardmask layer made of said first material on said backpolished polarization layer which structured hardmask layer adjoins said sacrificial plug and has at least one opening in said second region; forming at least one contact hole in said second region under said at least one opening in said second region, said at least one contact hole exposing a substrate

Abstract: A method for the integration of field-effect transistors for memory and logic applications in a semiconductor substrate is disclosed. The gate dielectric and a semiconductor layer are deposited over the whole area both in the logic region and in the memory region. From these layers, the gate electrodes in the memory region are formed, the source and drain regions are implanted and the memory region is covered in a planarizing manner with an insulation material. Afterward, the gate electrodes are formed from the semiconductor layer and the gate dielectric in the logic region.

Abstract: A power module includes at least one carrier body for mounting at least one power component thereon, and at least one energy storage component. For this purpose, a hybrid circuit is arranged as a thick film circuit on at least one of the carrier bodies, and the hybrid circuit includes at least one thick film resistor as a discharging resistor for discharging the at least one energy storage component. The power module is adapted for use as a power converter for electric motors.