Abstract: Methods and devices are discussed where a plurality of input signals having different phases are provided. From the input signals, a plurality of signal pairs are selected, and intermediate signals are generated based on the signal pairs. The intermediate signals are then combined.

Abstract: Methods and devices are discussed where a plurality of input signals having different phases are provided. From the input signals, a plurality of signal pairs are selected, and intermediate signals are generated based on the signal pairs. The intermediate signals are then combined.

Abstract: Representative implementations of devices and techniques provide reduced jitter for a controlled oscillator. An edge of a reference signal is injected at various points within the oscillator, and is replaced for an edge of the generated oscillation signal at the injection point.

Abstract: Representative implementations of devices and techniques provide reduced jitter and local phase detection for a controlled oscillator. An edge of a reference signal is injected at a point within the oscillator, and replaces an edge of the generated oscillation signal at the injection point. A phase difference of the injected reference signal and the oscillation signal is measured locally and is used to tune the oscillator.

Abstract: Representative implementations of devices and techniques provide reduced jitter and local phase detection for a controlled oscillator. An edge of a reference signal is injected at a point within the oscillator, and replaces an edge of the generated oscillation signal at the injection point. A phase difference of the injected reference signal and the oscillation signal is measured locally and is used to tune the oscillator.

Abstract: Representative implementations of devices and techniques provide reduced jitter for a controlled oscillator. An edge of a reference signal is injected at various points within the oscillator, and is replaced for an edge of the generated oscillation signal at the injection point.

Abstract: Representative implementations of devices and techniques provide a spread spectrum clocking signal. In a frequency synthesizer, a sequence of values may be generated and used to modulate a frequency of an input signal to the frequency synthesizer.

Abstract: A phase detector device having a modulo N operator coupled with an adder is disclosed. Furthermore, clock recovery devices using such a phase detector device are discussed.

Abstract: A phase detector device having a modulo N operator coupled with an adder is disclosed. Furthermore, clock recovery devices using such a phase detector device are discussed.

Abstract: Representative implementations of devices and techniques provide a spread spectrum clocking signal. In a frequency synthesizer, a sequence of values may be generated and used to modulate a frequency of an input signal to the frequency synthesizer.

Abstract: An apparatus for the controlled delay of an input signal includes a signal input for receiving an input signal. The input signal is supplied to a delay line with a multiplicity of delay elements. Outputs of the delay elements allow respective differently delayed phase signals to be tapped off. Furthermore, a register line with a multiplicity of register elements is provided. The register elements are each associated with one of the delay elements. Each of the register elements has a reset input and a clock input. The reset inputs are coupled to the signal input. The outputs of the delay elements are each coupled to the clock input of the register element associated therewith.

Abstract: An apparatus for the controlled delay of an input signal includes a signal input for receiving an input signal. The input signal is supplied to a delay line with a multiplicity of delay elements. Outputs of the delay elements allow respective differently delayed phase signals to be tapped off. Furthermore, a register line with a multiplicity of register elements is provided. The register elements are each associated with one of the delay elements. Each of the register elements has a reset input and a clock input. The reset inputs are coupled to the signal input. The outputs of the delay elements are each coupled to the clock input of the register element associated therewith.