Abstract: Time-critical actions of peripherals sharing a synchronous serial bus can be coordinated flexibly in real time by transmitting the messages through the bus well in advance of the scheduled execution time rather than “just in time.” The messages include an action code addressed to the peripheral's shadow register and a time-to-strobe, measured in bus-clock cycles, calculated by a time protocol engine in the system controller and addressed to the peripheral's counting register. The action code is stored in the shadow register while the counting register counts up or down to the time-to-strobe using the bus-clock signal. When the count reaches zero, the action code is written to the function-control register, triggering immediate execution of the action. Because the time-to-strobe can be any number of clock cycles within the counting register's capacity, the transmission timing is decoupled from the execution timing, relaxing transmission-timing constraints.

Abstract: Techniques and mechanisms to enable addressing of components accessed via a control interface. In an embodiment, a plurality of identifiers is logically split into first and second pools. The first pool is available for assigning to allow addressing of components while such components are active with respect to some functionality. The second pool is available for assigning to allow addressing of components while such components are passive with respect to some functionality. In another embodiment, different respective identifiers of the first pool pool are assigned each of first one or more of the plurality of components, and a respective identifier of the second pool is assigned to each of second one or more of the plurality of components. Any two of the second one or more components that have the same address default are assigned different respective identifiers of the second pool.

Abstract: Time-critical actions of peripherals sharing a synchronous serial bus can be coordinated flexibly in real time by transmitting the messages through the bus well in advance of the scheduled execution time rather than “just in time.” The messages include an action code addressed to the peripheral's shadow register and a time-to-strobe, measured in bus-clock cycles, calculated by a time protocol engine in the system controller and addressed to the peripheral's counting register. The action code is stored in the shadow register while the counting register counts up or down to the time-to-strobe using the bus-clock signal. When the count reaches zero, the action code is written to the function-control register, triggering immediate execution of the action. Because the time-to-strobe can be any number of clock cycles within the counting register's capacity, the transmission timing is decoupled from the execution timing, relaxing transmission-timing constraints.

Abstract: Techniques and mechanisms to enable addressing of components accessed via a control interface. In an embodiment, a plurality of identifiers is logically split into first and second pools. The first pool is available for assigning to allow addressing of components while such components are active with respect to some functionality. The second pool is available for assigning to allow addressing of components while such components are passive with respect to some functionality. In another embodiment, different respective identifiers of the first pool pool are assigned each of first one or more of the plurality of components, and a respective identifier of the second pool is assigned to each of second one or more of the plurality of components. Any two of the second one or more components that have the same address default are assigned different respective identifiers of the second pool.

Abstract: Described herein are devices and methods for implementing a transceiver with independently controlled components. The components may include a programmable digital portion, a dedicated digital portion, and an analog portion. Each independently controlled component includes a programmable controller that resides in the programmable digital portion of the component that controls components in the dedicated digital or analog portions using state transition information.

Abstract: A processing module, a processor circuit, an instruction set for processing data, and a method for synchronizing the processing of codes are provided. In an embodiment of the invention, a processing module for processing instructions, the instructions relating to user data and control data according to a communication protocol. The processing module includes a first processing circuit configured to process the instructions relating to the control data, and a second processing circuit configured to process the instructions relating to the user data.

Abstract: For example, a communication device may be provided comprising an oscillator configured to generate a reference signal; an accuracy determiner configured to determine information about an accuracy of a frequency of the reference signal; a signal detector configured to detect the presence of a radio signal; and a controller configured to control the signal detector based on the information.

Abstract: For example, a communication device may be provided comprising an oscillator configured to generate a reference signal; an accuracy determiner configured to determine information about an accuracy of a frequency of the reference signal; a signal detector configured to detect the presence of a radio signal; and a controller configured to control the signal detector based on the information.

Abstract: Described herein are devices and methods for implementing a transceiver with independently controlled components. The components may include a programmable digital portion, a dedicated digital portion, and an analog portion. Each independently controlled component includes a programmable controller that resides in the programmable digital portion of the component that controls components in the dedicated digital or analog portions using state transition information.

Abstract: The present invention provides a data processing apparatus having at least one dedicated data processing device (10) of a first type, a central data processing device (4) for controlling dedicated data processing devices (10, 12, 14), at least one data transmission channel (16) for transmitting data between the data processing devices (4, 10, 12, 14) and a data transmission device (6) for transmitting data between the data processing devices via the at least one data transmission channel (16) in a manner dependent on data transmission parameters, the data transmission parameters which are assigned to the at least one dedicated data processing device (10) of the first type being generated by the at least one dedicated data processing device (10) of the first type.

Abstract: A processing module, a processor circuit, an instruction set for processing data, and a method for synchronizing the processing of codes are provided. In an embodiment of the invention, a processing module for processing instructions, the instructions relating to user data and control data according to a communication protocol. The processing module includes a first processing circuit configured to process the instructions relating to the control data, and a second processing circuit configured to process the instructions relating to the user data.

Abstract: Receiver for Receiving Data Frames. According to one aspect, a receiver for receiving data frames which contain information data includes a signal input. Further, the receiver includes a data frame separator circuit for separating the signaling data from the information data. A switching device connects the data present at current input to a data output. A channel decoding circuit decodes the data which is present and generates signals which indicate whether the decoding has been carried out correctly. When correct decoding has taken place, a control circuit buffers all data and outputs a signal to the switching device to connect the buffered information data to the channel decoding circuit. When the signal indicates the correct decoding is received, the control circuit outputs the decoded information data.

Abstract: In a method for transporting (DMA_TASK(n), DMA_TASK(n+1)) data sections between a memory and a peripheral, a control signal (START(n+1)), which is used to ask a DMA controller (DMA) to transport (DMA_TASK(n+1)) a data section, is transmitted to the DMA controller, and information about the data transport operation (DMA_TASK(n+1)) to be carried out is then being loaded into the DMA controller, and the data is then being transported (DMA_TASK(n+1)) using the DMA controller.

Abstract: Receiver for receiving data frames which contain information data and signaling data, the signaling data comprising a data frame identifier and a decoding instruction for decoding the information data, having:

Abstract: A circuit for recording and playing back voice in digital mobile radio devices and a method for appropriately recording and playing back the voice. The circuit includes a transmit-end voice encoder, a receive-end voice decoder, a memory for the recorded signals, a further voice encoder whose output is connected to the memory, and a further voice decoder whose input is connected to the memory.

Abstract: A hip-joint endoprosthesis as a surface replacement for the proximal femur is proposed, which hip-joint endoprosthesis can be secured in the neck of the femur without cement.

Abstract: A circuit for recording and playing back voice in digital mobile radio devices and a method for appropriately recording and playing back the voice. The circuit includes a transmit-end voice encoder, a receive-end voice decoder, a memory for the recorded signals, a further voice encoder whose output is connected to the memory, and a further voice decoder whose input is connected to the memory.