Patents by Inventor Werner Juchmes
Werner Juchmes has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11043938Abstract: Disclosed aspects relate to a digital logic circuit. A clock generation circuitry has both a clock generation circuitry output and an inverter circuit to generate a derivative clock signal feature by inverting an array clock signal feature. A scannable storage element has both a scannable storage element output and a set of flip-flops. A memory array is connected with the scannable storage element output and the array clock signal feature. The digital logic circuit is configured to avoid a race violation.Type: GrantFiled: December 19, 2019Date of Patent: June 22, 2021Assignee: International Business Machines CorporationInventors: Harry Barowski, Werner Juchmes, Michael B. Kugel, Wolfgang Penth
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Patent number: 10984160Abstract: Circuit analysis and modification by receiving a first description of a circuit, the first description having a first level of detail, receiving a second description of the circuit, the second description having a second level of detail, performing a circuit simulation according to the first description, identifying an active node of the first description according to the simulation, and modifying the second description according to the active node.Type: GrantFiled: May 7, 2020Date of Patent: April 20, 2021Assignee: International Business Machines CorporationInventors: Martin Bernhard Schmidt, Alexander Fritsch, Werner Juchmes, Simon Brandl
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Publication number: 20200127649Abstract: Disclosed aspects relate to a digital logic circuit. A clock generation circuitry has both a clock generation circuitry output and an inverter circuit to generate a derivative clock signal feature by inverting an array clock signal feature. A scannable storage element has both a scannable storage element output and a set of flip-flops. A memory array is connected with the scannable storage element output and the array clock signal feature. The digital logic circuit is configured to avoid a race violation.Type: ApplicationFiled: December 19, 2019Publication date: April 23, 2020Inventors: Harry Barowski, Werner Juchmes, Michael B. Kugel, Wolfgang Penth
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Patent number: 10587248Abstract: Disclosed aspects relate to a digital logic circuit. A clock generation circuitry has both a clock generation circuitry output and an inverter circuit to generate a derivative clock signal feature by inverting an array clock signal feature. A scanable storage element has both a scanable storage element output and a set of flip-flops. A memory array is connected with the scanable storage element output and the array clock signal feature. The digital logic circuit is configured to avoid a race violation.Type: GrantFiled: January 24, 2017Date of Patent: March 10, 2020Assignee: International Business Machines CorporationInventors: Harry Barowski, Werner Juchmes, Michael B. Kugel, Wolfgang Penth
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Patent number: 10367481Abstract: Disclosed aspects relate to a digital logic circuit. A clock generation circuitry has both a clock generation circuitry output and an inverter circuit to generate a derivative clock signal feature by inverting an array clock signal feature. A scanable storage element has both a scanable storage element output and a set of flip-flops. A memory array is connected with the scanable storage element output and the array clock signal feature. The digital logic circuit is configured to avoid a race violation.Type: GrantFiled: February 20, 2018Date of Patent: July 30, 2019Assignee: International Business Machines CorporationInventors: Harry Barowski, Werner Juchmes, Michael B. Kugel, Wolfgang Penth
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Publication number: 20180212595Abstract: Disclosed aspects relate to a digital logic circuit. A clock generation circuitry has both a clock generation circuitry output and an inverter circuit to generate a derivative clock signal feature by inverting an array clock signal feature. A scanable storage element has both a scanable storage element output and a set of flip-flops. A memory array is connected with the scanable storage element output and the array clock signal feature. The digital logic circuit is configured to avoid a race violation.Type: ApplicationFiled: February 20, 2018Publication date: July 26, 2018Inventors: Harry Barowski, Werner Juchmes, Michael B. Kugel, Wolfgang Penth
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Publication number: 20180212594Abstract: Disclosed aspects relate to a digital logic circuit. A clock generation circuitry has both a clock generation circuitry output and an inverter circuit to generate a derivative clock signal feature by inverting an array clock signal feature. A scanable storage element has both a scanable storage element output and a set of flip-flops. A memory array is connected with the scanable storage element output and the array clock signal feature. The digital logic circuit is configured to avoid a race violation.Type: ApplicationFiled: January 24, 2017Publication date: July 26, 2018Inventors: Harry Barowski, Werner Juchmes, Michael B. Kugel, Wolfgang Penth
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Patent number: 9666278Abstract: A memory apparatus includes a content addressable memory, CAM, cell block including CAM cells and a random access memory (RAM), cell block including RAM cells. A geometric footprint of each of the CAM cells has a side bigger than a side of a geometric footprint of each of the RAM cells, where the sides of the CAM cells and the RAM cells are parallel to each other. The apparatus is configured to translate an input keyword at an input of the CAM cell block to an output word at an output of the RAM cell block when the keyword at the input of the CAM cell block is stored in the CAM cell block. The CAM cell block is split into a first part and a second part of the CAM cells.Type: GrantFiled: September 16, 2015Date of Patent: May 30, 2017Assignee: International Business Machines CorporationInventors: Alexander Fritsch, Werner Juchmes, Shankar Kalyanasundaram, Rolf Sautter
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Patent number: 9431096Abstract: A memory device having a plurality of banks of memory cells may be provided. Each memory cells may be interconnected via a local write bit-line and a complementary local write bit-line to a local write bit-line buffer circuit. The local write bit-line buffer circuit may be connected via a global write bit-line and a complementary one to a negative bias write assist circuit. The memory device may also comprise an address decoder separately connected to the local write bit-line buffer circuits. The address decoder may comprise a generating unit for enabling exactly one local write enable signal for a respective one of said local write bit-line buffer circuits. The local write bit-line buffer circuit may be adapted for generating local write data on said local write bit-line in response to receiving global write data on said global write bit-line when its local write enable signal is enabled.Type: GrantFiled: November 17, 2015Date of Patent: August 30, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Alexander Fritsch, Werner Juchmes, Michael B. Kugel, Rolf Sautter
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Publication number: 20160099053Abstract: A memory apparatus includes a content addressable memory, CAM, cell block including CAM cells and a random access memory (RAM), cell block including RAM cells. A geometric footprint of each of the CAM cells has a side bigger than a side of a geometric footprint of each of the RAM cells, where the sides of the CAM cells and the RAM cells are parallel to each other. The apparatus is configured to translate an input keyword at an input of the CAM cell block to an output word at an output of the RAM cell block when the keyword at the input of the CAM cell block is stored in the CAM cell block. The CAM cell block is split into a first part and a second part of the CAM cells.Type: ApplicationFiled: September 16, 2015Publication date: April 7, 2016Inventors: Alexander Fritsch, Werner Juchmes, Shankar Kalyanasundaram, Rolf Sautter
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Publication number: 20130128684Abstract: A memory array can be arranged with header devices to reduce leakage. The header devices are coupled with a decoder to receive at least a first portion of a memory address indication and are coupled to receive current from a power supply. Each of header devices is adapted to provide power from the power supply to a set of the wordline drivers corresponding to a bank indicated with the first portion of the memory address indication. Each of the logic devices is coupled to receive at least a second portion of the memory address indication from a decoder. Each of the logic devices is coupled to activate the wordline drivers coupled with those of the wordlines indicated with the second portion of the memory address indication.Type: ApplicationFiled: May 8, 2012Publication date: May 23, 2013Applicant: International Business Machines CorporationInventors: Stefan Buettner, Thomas Froehnel, Werner Juchmes, Rolf Sautter, Victor Zyuban
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Patent number: 8422313Abstract: In a circuit that reduces power consumption in an array system of memory cells accessible in parallel, a local evaluation circuit is connected to a memory cell and a global bit line of the array system of memory cells. A selection circuitry splits the global bit line into an upper part and a lower part of the global bit line. The selection circuitry is adapted to receive an early set prediction signal and to connect the upper part of the global bit line to the lower part of the global bit line based on the early set prediction signal. The early set prediction signal indicates whether a set of memory cells, which include the memory cell, is being read. The circuit also includes a N:1 multiplexer connected to the lower part of the global bit line to receive the lower part of the global bit line as input.Type: GrantFiled: October 28, 2011Date of Patent: April 16, 2013Assignee: International Business Machines CorporationInventors: Stefan Buettner, David A. Hrusecky, Werner Juchmes, Wolfgang Penth, Rolf Sautter
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Publication number: 20120155188Abstract: In a circuit that reduces power consumption in an array system of memory cells accessible in parallel, a local evaluation circuit is connected to a memory cell and a global bit line of the array system of memory cells. A selection circuitry splits the global bit line into an upper part and a lower part of the global bit line. The selection circuitry is adapted to receive an early set prediction signal and to connect the upper part of the global bit line to the lower part of the global bit line based on the early set prediction signal. The early set prediction signal indicates whether a set of memory cells, which include the memory cell, is being read. The circuit also includes a N:1 multiplexer connected to the lower part of the global bit line to receive the lower part of the global bit line as input.Type: ApplicationFiled: October 28, 2011Publication date: June 21, 2012Applicant: International Business Machines CorporationInventors: Stefan Buettner, David A. Hrusecky, Werner Juchmes, Wolfgang Penth, Rolf Sautter
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Patent number: 7844871Abstract: A method for testing memory elements of an integrated circuit with an array built in self test (ABIST) comprises providing an ABIST interface to interface between an ABIST engine and a plurality of latches of a memory element under test, providing a multiplex (MUX) stage adjacent a scan input port of each latch, providing functional signal inputs to a data input port of the latches, setting the latches to an ABIST mode by activating an ABIST enable signal and delivering the ABIST enable signal to each of the latches, generating a plurality of ABIST test signals with the ABIST engine, applying the ABIST test signals in parallel to the scan input ports of the latches, determining whether one or more test patterns have been executed, and setting the latches to a normal run mode by deactivating the ABIST enable signal.Type: GrantFiled: November 11, 2008Date of Patent: November 30, 2010Assignee: International Business Machines CorporationInventors: Uwe Brandt, Stefan Buettner, Werner Juchmes, Juergen Pille
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Publication number: 20100122128Abstract: A method for testing memory elements of an integrated circuit with an array built in self test (ABIST) comprises providing an ABIST interface to interface between an ABIST engine and a plurality of latches of a memory element under test, providing a multiplex (MUX) stage adjacent a scan input port of each latch, providing functional signal inputs to a data input port of the latches, setting the latches to an ABIST mode by activating an ABIST enable signal and delivering the ABIST enable signal to each of the latches, generating a plurality of ABIST test signals with the ABIST engine, applying the ABIST test signals in parallel to the scan input ports of the latches, determining whether one or more test patterns have been executed, and setting the latches to a normal run mode by deactivating the ABIST enable signal.Type: ApplicationFiled: November 11, 2008Publication date: May 13, 2010Applicant: International Business Machines CorporationInventors: Uwe Brandt, Stefan Buettner, Werner Juchmes, Juergen Pille
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Patent number: 7558138Abstract: A method for bypassing a memory array in a circuit having a global bit line, a test port configured to output a logic test, a memory portion connected to the global bit line via a word line, a header device being connected to the global bit line via a pre-charge signal, the header device being configured to recharge the global bit line. A gating signal is sent to a gating device connected to the header device. The gating device is switched to a test mode upon receipt of the gating signal. The bypass data signal is sent to an evaluating device connected to the gating device, the evaluating device being configured to output a logic test. The logic test is output through the test port upon receipt of bypass data signal.Type: GrantFiled: September 30, 2008Date of Patent: July 7, 2009Assignee: International Business Machines CorporationInventors: Sebastian Ehrenreich, Werner Juchmes, Atnje Mueller, Silke Salewski