Abstract: Methods and apparatus are described. An apparatus includes a hexagonal oxide substrate and a III-nitride semiconductor structure adjacent the hexagonal oxide substrate. The III-nitride semiconductor structure includes a light emitting layer between an n-type region and a p-type region. The hexagonal oxide substrate has an in-plane coefficient of thermal expansion (CTE) within 30% of a CTE of the III-nitride semiconductor structure.

Abstract: Methods and apparatus are described. An apparatus includes a hexagonal oxide substrate and a III-nitride semiconductor structure adjacent the hexagonal oxide substrate. The III-nitride semiconductor structure includes a light emitting layer between an n-type region and a p-type region. The hexagonal oxide substrate has an in-plane coefficient of thermal expansion (CTE) within 30% of a CTE of the III-nitride semiconductor structure.

Abstract: A device includes a substrate (10) and a III-nitride structure (15) grown on the substrate, the III-nitride structure comprising a light emitting layer (16) disposed between an n-type region (14) and a p-type region (18). The substrate is a RA03 (MO)n where R is one of a trivalent cation: Sc, In, Y and a lanthanide; A is one of a trivalent cation: Fe (III), Ga and Al; M is one for a divalent cation: Mg, Mn, Fe (II), Co, Cu, Zn and Cd; and n is an integer?1. The substrate has an inplane lattice constant asubstrate. At lease one III-nitride layer in the III-nitride structure has a bulk lattice constant alayer such that [(|asubstrate?alayer|)/asubstrate]*100% is no more than 1%.

Abstract: Methods and apparatus are described. An apparatus includes a hexagonal oxide substrate and a III-nitride semiconductor structure adjacent the hexagonal oxide substrate. The III-nitride semiconductor structure includes a light emitting layer between an n-type region and a p-type region. The hexagonal oxide substrate has an in-plane coefficient of thermal expansion (CTE) within 30% of a CTE of the III-nitride semiconductor structure.

Abstract: Methods and apparatus are described. An apparatus includes a hexagonal oxide substrate and a III-nitride semiconductor structure adjacent the hexagonal oxide substrate. The III-nitride semiconductor structure includes a light emitting layer between an n-type region and a p-type region. The hexagonal oxide substrate has an in-plane coefficient of thermal expansion (CTE) within 30% of a CTE of the III-nitride semiconductor structure.

Abstract: In embodiments of the invention, a semiconductor structure comprising a III-nitride light emitting layer disposed between an n-type region and a p-type region is grown on a substrate. The substrate is a non-III-nitride material. The substrate has an in-plane lattice constant asubstrate. At least one III-nitride layer in the semiconductor structure has a bulk lattice constant alayer and [(|asubstrate?alayer|)/asubstrate]*100% is no more than 1%. A surface of the substrate opposite the surface on which the semiconductor structure is grown is textured.

Abstract: In embodiments of the invention, a semiconductor structure comprising a III-nitride light emitting layer disposed between an n-type region and a p-type region is grown on a substrate. The substrate is a non-III-nitride material. The substrate has an in-plane lattice constant asubstrate. At least one III-nitride layer in the semiconductor structure has a bulk lattice constant alayer and [(|asubstrate?alayer|)/asubstrate]*100% is no more than 1%. A surface of the substrate opposite the surface on which the semiconductor structure is grown is textured.

Abstract: In embodiments of the invention, a semiconductor structure comprising a III-nitride light emitting layer disposed between an n-type region and a p-type region is grown on a substrate. The substrate is a non-III-nitride material. The substrate has an in-plane lattice constant asubstrate. At least one III-nitride layer in the semiconductor structure has a bulk lattice constant alayer and [(|asubstrate?alayer|)/asubstrate]100% is no more than 1%. A surface of the substrate opposite the surface on which the semiconductor structure is grown is textured.

Abstract: A device includes a substrate (10) and a III-nitride structure (15) grown on the substrate, the III-nitride structure comprising a light emitting layer (16) disposed between an n-type region (14) and a p-type region (18). The substrate is a RAO3 (MO)n where R is one of a trivalent cation: Sc, In, Y and a lanthanide; A is one of a trivalent cation: Fe (III), Ga and Al; M is one for a divalent cation: Mg, Mn, Fe (II), Co, Cu, Zn and Cd; and n is an integer ?1. The substrate has an inplane lattice constant asubstrate. At lease one III-nitride layer in the III-nitride structure has a bulk lattice constant alayer such that [(|asubstrate?alayer|)/asubstrate]*100% is no more than 1%.

Abstract: In embodiments of the invention, a semiconductor structure comprising a III-nitride light emitting layer disposed between an n-type region and a p-type region is grown on a substrate. The substrate is a non-III-nitride material. The substrate has an in-plane lattice constant asubstrate. At least one III-nitride layer in the semiconductor structure has a bulk lattice constant alayer and [(|asubstrate?alayer|)/asubstrate]100% is no more than 1%. A surface of the substrate opposite the surface on which the semiconductor structure is grown is textured.