Abstract: A computer having a plurality of data bus controllers, a plurality of grouped controller ports and a plurality of connection elements for connecting the controllers to the ports, wherein each controller has a maximum available controller bandwidth; characterized in that the connection elements are arranged such that each controller is connected to ports from different groups such that data pathways between the controllers and the ports are not variable, and a maximum port group bandwidth available to each port group cannot be changed, irrespective of a bandwidth demand at said each port group.

Abstract: A process and apparatus for configuring a motherboard or host computer (3) to operate direct memory transfer mode, such as Ultra-DMA or Ultra-ATA, in accordance with the particular type of cable—IDE or 40-conductor cable being used. The 80-conductor cable has one particular conductor which is cut between the host connector and the device connectors and which corresponds to a terminal which the device releases when it receives a reset pulse. On the host side the terminal is internally connected to ground. A sampling of the logical state carried by the particular terminal is performed during a reset pulse transmitted to the device(s), in order to determine the type of cable, and configure the Ultra-DMA mode accordingly. The invention is well adapted for the 80-conductor detection by testing pin 34 carrying the PDIAG# signal.

Abstract: A computer having a plurality of data bus controllers, a plurality of grouped controller ports and a plurality of connection elements for connecting the controllers to the ports;