Abstract: Integrated circuit package comprising a power supply distribution wiring and a chip interconnection signal wiring both formed on the top surface of a passive semiconductor interconnection carrier (2) in which a power supply decoupling capacitor is implemented.Spaced wells (4) of a first conductivity type are provided in the surface of said carrier of a second conductivity type.The power supply distribution wiring comprises first and second conductive lines (5,6) within a first wiring level (WL1).Said first conductive lines (5) are deposited on the surface areas of said wells (4) in an ohmic contact relationship and said second conductive lines (6) are deposited on the surface areas of said carrier (2) between said wells (4) in an ohmic contact relationship.Said first and second conductive lines are connected to first and second terminals of the power supply, respectively, so that the junction capacitance between said wells (4) and the carrier material (2) embedding said wells forms said decoupling capacitor.

Abstract: Integrated circuit package comprising a power supply distribution wiring and a chip interconnection signal wiring both formed on the top surface of a passive semiconductor interconnection carrier (2) in which a power supply decoupling capacitor is implemented.Spaced wells (4) of a first conductivity type are provided in the surface of said carrier of a second conductivity type.The power supply distribution wiring comprises first and second conductive lines (5,6) within a first wiring level (WL1).Said first conductive lines (5) are deposited on the surface areas of said wells (4) in an ohmic contact relationship and said second conductive lines (6) are deposited on the surface areas of said carrier (2) between said wells (4) in an ohmic contact relationship.Said first and second conductive lines are connected to first second terminals of the power supply, respectively, so that the junction capacitance between said wells (4) and the carrier material (2) embedding said wells forms said decoupling capacitor.

Abstract: This invention relates to a field effect transistor level converter for converting bipolar transistor logic levels to field effect transistor logic levels. First and second field effect transistors have their source and gate electrodes connected in common. The bipolar input signal is received at the common source connection while the gate electrodes receive a fixed reference potential that is equal to the threshold voltage VT plus the lowest possible high binary level of the bipolar input logic. The drain electrode of the first field effect transistor is connected to the output terminal of the level converter and the source electrode of a source follower transistor. The drain electrode of the second transistor is connected to a load device and to the gate of the source follower transistor which has its drain electrode connected to VH. This arrangement produces at the first output terminal a potential swing of approximately 0 to 7 volts in response to an input signal in the range of 0.8 to 2.0 volts.

Abstract: a field effect transistor having a channel width of such small dimension that threshold voltage becomes inversely related to channel width allowing the fabrication of field effect transistors of differing threshold voltages while using the same process steps. Reduced threshold voltage due to prior art "short channel length" effect may be offset by the presently disclosed narrow channel width effect. Desired chanel impedance values are achieved independently of threshold voltage influence due to narrow channel width effect by the provision of parallel-connected field effect transistors of the same channel length whose total channel widths yield a desired net width-to-length ratio.