Patents by Inventor Werner Rausch
Werner Rausch has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200364316Abstract: Methods and systems for a circuit similarity metric for semiconductor testsite coverage. One or more unique values for each of a set of measures for each circuit layout of a plurality of circuit layouts are identified and a pairwise comparison across the set of measures is conducted for a selected pair of the plurality of circuit layouts to derive a similarity score for the selected pair of circuit layouts. The similarity score is incremented for the selected pair in response to the selected pair of circuit layouts sharing a same unique value and the similarity score is decremented for the selected pair in response to one circuit layout of the selected pair of circuit layouts having a unique value that the other circuit layout of the selected pair does not contain.Type: ApplicationFiled: May 14, 2019Publication date: November 19, 2020Inventors: Rasit Onur Topaloglu, Dureseti Chidambarrao, Werner A. Rausch, Leon Stok
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Patent number: 10839133Abstract: Methods and systems for a circuit similarity metric for semiconductor testsite coverage. One or more unique values for each of a set of measures for each circuit layout of a plurality of circuit layouts are identified and a pairwise comparison across the set of measures is conducted for a selected pair of the plurality of circuit layouts to derive a similarity score for the selected pair of circuit layouts. The similarity score is incremented for the selected pair in response to the selected pair of circuit layouts sharing a same unique value and the similarity score is decremented for the selected pair in response to one circuit layout of the selected pair of circuit layouts having a unique value that the other circuit layout of the selected pair does not contain.Type: GrantFiled: May 14, 2019Date of Patent: November 17, 2020Assignee: International Business Machines CorporationInventors: Rasit Onur Topaloglu, Dureseti Chidambarrao, Werner A. Rausch, Leon Stok
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Patent number: 10552758Abstract: A vertical q-capacitor includes a trench in a substrate through a layer of superconducting material. A superconductor is deposited in the trench forming a first film on a first surface, a second film on a second surface, and a third film of the superconductor on a third surface of the trench. The first and second surfaces are substantially parallel, and the third surface in the trench separates the first and second surfaces. A dielectric is exposed below the third film by etching. A first coupling is formed between the first film and a first contact, and a second coupling is formed between the second film and a second contact in a superconducting quantum logic circuit. The first and second couplings cause the first and second films to operate as the vertical q-capacitor that maintains integrity of data in the superconducting quantum logic circuit within a threshold level.Type: GrantFiled: April 3, 2019Date of Patent: February 4, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jared Barney Hertzberg, Werner A. Rausch, Sami Rosenblatt, Rasit O. Topaloglu
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Patent number: 10445651Abstract: A vertical q-capacitor includes a trench in a substrate through a layer of superconducting material. A superconductor is deposited in the trench forming a first film on a first surface, a second film on a second surface, and a third film of the superconductor on a third surface of the trench. The first and second surfaces are substantially parallel, and the third surface in the trench separates the first and second surfaces. A dielectric is exposed below the third film by etching. A first coupling is formed between the first film and a first contact, and a second coupling is formed between the second film and a second contact in a superconducting quantum logic circuit. The first and second couplings cause the first and second films to operate as the vertical q-capacitor that maintains integrity of data in the superconducting quantum logic circuit within a threshold level.Type: GrantFiled: June 27, 2018Date of Patent: October 15, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jared Barney Hertzberg, Werner A. Rausch, Sami Rosenblatt, Rasit O. Topaloglu
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Publication number: 20190228334Abstract: A vertical q-capacitor includes a trench in a substrate through a layer of superconducting material. A superconductor is deposited in the trench forming a first film on a first surface, a second film on a second surface, and a third film of the superconductor on a third surface of the trench. The first and second surfaces are substantially parallel, and the third surface in the trench separates the first and second surfaces. A dielectric is exposed below the third film by etching. A first coupling is formed between the first film and a first contact, and a second coupling is formed between the second film and a second contact in a superconducting quantum logic circuit. The first and second couplings cause the first and second films to operate as the vertical q-capacitor that maintains integrity of data in the superconducting quantum logic circuit within a threshold level.Type: ApplicationFiled: April 3, 2019Publication date: July 25, 2019Applicant: International Business Machines CorporationInventors: Jared Barney Hertzberg, Werner A. Rausch, Sami Rosenblatt, Rasit O. Topaloglu
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Publication number: 20190130302Abstract: A vertical q-capacitor includes a trench in a substrate through a layer of superconducting material. A superconductor is deposited in the trench forming a first film on a first surface, a second film on a second surface, and a third film of the superconductor on a third surface of the trench. The first and second surfaces are substantially parallel, and the third surface in the trench separates the first and second surfaces. A dielectric is exposed below the third film by etching. A first coupling is formed between the first film and a first contact, and a second coupling is formed between the second film and a second contact in a superconducting quantum logic circuit. The first and second couplings cause the first and second films to operate as the vertical q-capacitor that maintains integrity of data in the superconducting quantum logic circuit within a threshold level.Type: ApplicationFiled: June 27, 2018Publication date: May 2, 2019Applicant: International Business Machines CorporationInventors: Jared Barney Hertzberg, Werner A. Rausch, Sami Rosenblatt, Rasit O. Topaloglu
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Patent number: 10068184Abstract: A vertical q-capacitor includes a trench in a substrate through a layer of superconducting material. A superconductor is deposited in the trench forming a first film on a first surface, a second film on a second surface, and a third film of the superconductor on a third surface of the trench. The first and second surfaces are substantially parallel, and the third surface in the trench separates the first and second surfaces. A dielectric is exposed below the third film by etching. A first coupling is formed between the first film and a first contact, and a second coupling is formed between the second film and a second contact in a superconducting quantum logic circuit. The first and second couplings cause the first and second films to operate as the vertical q-capacitor that maintains integrity of data in the superconducting quantum logic circuit within a threshold level.Type: GrantFiled: October 27, 2017Date of Patent: September 4, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jared Barney Hertzberg, Werner A. Rausch, Sami Rosenblatt, Rasit O. Topaloglu
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Patent number: 9812394Abstract: An eFuse device on a substrate is formed on a substrate used for an integrated circuit. A semiconductor structure is created from a semiconductor layer deposited over the substrate. A mask layer is patterned over the semiconductor structure such that a first region of the semiconductor structure is exposed and a second region of the semiconductor structure is protected by the mask layer. Next, a self-limiting etch is performed on the exposed areas in the first region of the semiconductor structure, producing a first faceted region of the semiconductor structure in the first region. The semiconductor in the first faceted region has a minimum, nonzero thickness at a point where two semiconductor facet planes meet which is thinner than a thickness of semiconductor in the second region of the semiconductor structure is protected by the mask layer. The first faceted region is used as a link structure in the eFuse device.Type: GrantFiled: October 12, 2015Date of Patent: November 7, 2017Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Ali Khakifirooz, Juntao Li, Werner A Rausch
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Publication number: 20170103947Abstract: An eFuse device on a substrate is formed on a substrate used for an integrated circuit. A semiconductor structure is created from a semiconductor layer deposited over the substrate. A mask layer is patterned over the semiconductor structure such that a first region of the semiconductor structure is exposed and a second region of the semiconductor structure is protected by the mask layer. Next, a self-limiting etch is performed on the exposed areas in the first region of the semiconductor structure, producing a first faceted region of the semiconductor structure in the first region. The semiconductor in the first faceted region has a minimum, nonzero thickness at a point where two semiconductor facet planes meet which is thinner than a thickness of semiconductor in the second region of the semiconductor structure is protected by the mask layer. The first faceted region is used as a link structure in the eFuse device.Type: ApplicationFiled: October 12, 2015Publication date: April 13, 2017Inventors: Kangguo Cheng, Ali Khakifirooz, Juntao Li, Werner A Rausch
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Patent number: 9437496Abstract: A semiconductor device such as a FinFET includes a plurality of fins formed upon a substrate and a gate covering a portion of the fins. Diamond-shaped volumes are formed on the sidewalls of the fins by epitaxial growth which may be limited to avoid merging of the volumes or where the epitaxy volumes have merged. Because of the difficulties in managing merging of the diamond-shaped volumes, a controlled merger of the diamond-shaped volumes includes depositing an amorphous semiconductor material upon the diamond-shaped volumes and a crystallization process to crystallize the deposited semiconductor material on the diamond-shaped volumes to fabricate controllable and uniformly merged source drain.Type: GrantFiled: June 1, 2015Date of Patent: September 6, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Michael P. Chudzik, Brian J. Greene, Edward P. Maciejewski, Kevin McStay, Shreesh Narasimha, Chengwen Pei, Werner A. Rausch
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Publication number: 20150333145Abstract: Embodiments of the present invention provide a finFET and method of fabrication to achieve advantages of both merged and unmerged fins. A first step of epitaxy is performed with either partial diamond or full diamond growth. This is followed by a second step of deposition of a semiconductor cap region on the finFET source/drain area using a directional deposition process, followed by an anneal to perform Solid Phase Epitaxy or poly recrystalization. As a result, the fins remain unmerged, but the epitaxial volume is increased to provide reduced contact resistance. Embodiments of the present invention allow a narrower fin pitch, which enables increased circuit density on an integrated circuit.Type: ApplicationFiled: May 15, 2014Publication date: November 19, 2015Applicant: International Business Machines CorporationInventors: Michael P. Chudzik, Brian J. Greene, Edward P. Maciejewski, Kevin McStay, Shreesh Narasimha, Chengwen Pei, Werner A. Rausch
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Patent number: 9029862Abstract: A trench is formed in a semiconductor substrate, and is filled with a node dielectric layer and at least one conductive material fill portion that functions as an inner electrode. The at least one conductive material fill portion includes a doped polycrystalline semiconductor fill portion. A gate stack for an access transistor is formed on the semiconductor substrate, and a gate spacer is formed around the gate stack. A source/drain trench is formed between an outer sidewall of the gate spacer and a sidewall of the doped polycrystalline semiconductor fill portion. An epitaxial source region and a polycrystalline semiconductor material portion are simultaneously formed by a selective epitaxy process such that the epitaxial source region and the polycrystalline semiconductor material portion contact each other without a gap therebetween. The polycrystalline semiconductor material portion provides a robust low resistance conductive path between the source region and the inner electrode.Type: GrantFiled: May 24, 2013Date of Patent: May 12, 2015Assignee: International Business Machines CorporationInventors: Karen A. Nummy, Chengwen Pei, Werner A. Rausch, Geng Wang
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Patent number: 8680617Abstract: Disclosed is an SOI device on a bulk silicon layer which has an FET region, a body contact region and an STI region. The FET region is made of an SOI layer and an overlying gate. The STI region includes a first STI layer separating the SOI device from an adjacent SOI device. The body contact region includes an extension of the SOI layer, a second STI layer on the extension and a body contact in contact with the extension. The first and second STI layers are contiguous and of different thicknesses so as to form a split level STI.Type: GrantFiled: October 6, 2009Date of Patent: March 25, 2014Assignee: International Business Machines CorporationInventors: Ying Li, Shreesh Narasimha, Werner A. Rausch
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Publication number: 20130260520Abstract: A trench is formed in a semiconductor substrate, and is filled with a node dielectric layer and at least one conductive material fill portion that functions as an inner electrode. The at least one conductive material fill portion includes a doped polycrystalline semiconductor fill portion. A gate stack for an access transistor is formed on the semiconductor substrate, and a gate spacer is formed around the gate stack. A source/drain trench is formed between an outer sidewall of the gate spacer and a sidewall of the doped polycrystalline semiconductor fill portion. An epitaxial source region and a polycrystalline semiconductor material portion are simultaneously formed by a selective epitaxy process such that the epitaxial source region and the polycrystalline semiconductor material portion contact each other without a gap therebetween. The polycrystalline semiconductor material portion provides a robust low resistance conductive path between the source region and the inner electrode.Type: ApplicationFiled: May 24, 2013Publication date: October 3, 2013Inventors: Karen A. Nummy, Chengwen Pei, Werner A. Rausch, Geng Wang
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Patent number: 8507915Abstract: A trench is formed in a semiconductor substrate, and is filled with a node dielectric layer and at least one conductive material fill portion that functions as an inner electrode. The at least one conductive material fill portion includes a doped polycrystalline semiconductor fill portion. A gate stack for an access transistor is formed on the semiconductor substrate, and a gate spacer is formed around the gate stack. A source/drain trench is formed between an outer sidewall of the gate spacer and a sidewall of the doped polycrystalline semiconductor fill portion. An epitaxial source region and a polycrystalline semiconductor material portion are simultaneously formed by a selective epitaxy process such that the epitaxial source region and the polycrystalline semiconductor material portion contact each other without a gap therebetween. The polycrystalline semiconductor material portion provides a robust low resistance conductive path between the source region and the inner electrode.Type: GrantFiled: November 30, 2011Date of Patent: August 13, 2013Assignee: International Business Machines CorporationInventors: Karen A. Nummy, Chengwen Pei, Werner A. Rausch, Geng Wang
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Publication number: 20130134490Abstract: A trench is formed in a semiconductor substrate, and is filled with a node dielectric layer and at least one conductive material fill portion that functions as an inner electrode. The at least one conductive material fill portion includes a doped polycrystalline semiconductor fill portion. A gate stack for an access transistor is formed on the semiconductor substrate, and a gate spacer is formed around the gate stack. A source/drain trench is formed between an outer sidewall of the gate spacer and a sidewall of the doped polycrystalline semiconductor fill portion. An epitaxial source region and a polycrystalline semiconductor material portion are simultaneously formed by a selective epitaxy process such that the epitaxial source region and the polycrystalline semiconductor material portion contact each other without a gap therebetween. The polycrystalline semiconductor material portion provides a robust low resistance conductive path between the source region and the inner electrode.Type: ApplicationFiled: November 30, 2011Publication date: May 30, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Karen A. Nummy, Chengwen Pei, Werner A. Rausch, Geng Wang
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Patent number: 8222702Abstract: The present invention provides an improved CMOS diode structure with dual gate conductors. Specifically, a substrate comprising a first n-doped region and a second p-doped region is formed. A third region of either n-type or p-type conductivity is located between the first and second regions. A first gate conductor of n-type conductivity and a second gate conductor of p-type conductivity are located over the substrate and adjacent to the first and second regions, respectively. Further, the second gate conductor is spaced apart and isolated from the first gate conductor by a dielectric isolation structure. An accumulation region with an underlying depletion region can be formed in such a diode structure between the third region and the second or the first region, and such an accumulation region preferably has a width that is positively correlated with that of the second or the first gate conductor.Type: GrantFiled: June 14, 2010Date of Patent: July 17, 2012Assignee: International Business Machines CorporationInventors: David M. Onsongo, Werner Rausch, Haining S. Yang
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Patent number: 8067805Abstract: A method of forming a field effect transistor creates shallower and sharper junctions, while maximizing dopant activation in processes that are consistent with current manufacturing techniques. More specifically, the invention increases the oxygen content of the top surface of a silicon substrate. The top surface of the silicon substrate is preferably cleaned before increasing the oxygen content of the top surface of the silicon substrate. The oxygen content of the top surface of the silicon substrate is higher than other portions of the silicon substrate, but below an amount that would prevent epitaxial growth. This allows the invention to epitaxially grow a silicon layer on the top surface of the silicon substrate. Further, the increased oxygen content substantially limits dopants within the epitaxial silicon layer from moving into the silicon substrate.Type: GrantFiled: June 4, 2008Date of Patent: November 29, 2011Assignee: International Business Machines CorporationInventors: Huajie Chen, Omer H. Dokumaci, Oleg G. Gluschenkov, Werner A. Rausch
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Patent number: 8017483Abstract: The present invention provides a method of forming asymmetric field-effect-transistors.Type: GrantFiled: June 29, 2009Date of Patent: September 13, 2011Assignee: International Business Machines CorporationInventors: Gregory G. Freeman, Shreesh Narasimha, Ning Su, Hasan M. Nayfeh, Nivo Rovedo, Werner A. Rausch, Jian Yu
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Patent number: 7981751Abstract: A semiconductor structure including at least one transistor is provided which has a stressed channel region that is a result of having a stressed layer present atop a gate conductor that includes a stack comprising a bottom polysilicon (polySi) layer and a top metal semiconductor alloy (i.e., metal silicide) layer. The stressed layer is self-aligned to the gate conductor. The inventive structure also has a reduced external parasitic S/D resistance as a result of having a metallic contact located atop source/drain regions that include a surface region comprised of a metal semiconductor alloy. The metallic contact is self-aligned to the gate conductor.Type: GrantFiled: September 24, 2009Date of Patent: July 19, 2011Assignee: International Business Machines CorporationInventors: Huilong Zhu, Werner Rausch