Abstract: A method for controlling a device for metering granular material and a metering device for metering granular material comprises a feed for the granular material from a container into a metering chamber. A metering piston can be actuated by a control device such that a gap between the feed and the metering chamber is opened by a predefined first distance and a second distance which is greater than the first distance. At least one sensor is arranged in a delivery line leading away from the metering chamber and is connected to the control device so that the metering piston can be actuated for a predefined duration such that the gap between the feed for the granular material and the metering chamber can be opened by the second distance if a blockage of the granular material is detected by the at least one sensor, so that the blockage is dispersed.

Abstract: According to an embodiment of the invention, the received signal of a level sensor is sampled at discrete times, and the sampled values are digitised. New values are obtained from the digitised sample values by rotating the phase through a predetermined angle, which new values are then used together with the digital sample values to calculate the envelope curve.

Abstract: A digital deemphasis circuit for the BTSC multichannel television standard includes a square-root extractor, a digital filter having the transfer function F(z)=(b-ac)/(z+a), where a, b and c are constants that determine the frequency response of the digital filter. The digital deemphasis circuit further includes a subcircuit that transforms the output signal from the square-root extractor into three quantities w1, w2, w3 that are applied as multiplicands to three multipliers to control the operation of the deemphasis circuit.

Abstract: In a pulse-density D/A or A/D converter, improved averaging of a pulse-density-modulated (PDM) signal in the presence of a jittering clock signal is achieved by applying the PDM signal to the serial input of an n-stage shift register whose parallel output serves to control n state signals. The shift register is driven by the clock signal. The n state signals are combined into a sum signal which feeds a low-pass filter. In preferred embodiments, the n state signals are weighted and/or isolated from the respective previous state and the following state by means of gate circuits.

Abstract: An arithmetic logic unit (ALU) of a digital processor includes a multiplier to which a first data word A and a second data word B are fed as input data from a data memory. A third data word C, also coming from the data memory, is fed through a barrel shifter, whose shift number is q. The output of the barrel shifter is fed to one input of an adder having its other input connected to the output of the multiplier. The output of the adder provides a fourth data word D, which is written into the data memory. All movements of data necessary to form the fourth data word D are defined of a single program instruction.

Abstract: In digital-to-analog converters with "rotating" current sources for converting an n-bit binary signal to an analog output signal, a single cyclic shift register is replaced by m cyclic shift register portions each having p=(2.sup.n -1)/m inputs, and the n-digit binary signal to be converted is changed into the thermometer code by means of a code converter. The middle output of the code converter and equal numbers of code converter outputs on both sides thereof are connected to one of the shift register portions. According to the same rule, the code converter outputs located further from the middle are connected to the other shift register portions. Thus, a clock signal serving as a shift signal for the shift register portions only needs to have a frequency which is p times that of the sampling signal with which an, e.g., analog, audio signal is digitized.

Abstract: A correction circuit for a digital signal pair having an in-phase signal and a quadrature signal includes a value determining stage and an error-detecting stage. The value-determining stage determines a maximum value and a minimum value for the in-phase signal, a maximum value and a minimum value for the quadrature signal, and two held values for the quadrature signal that correspond to the maximum and minimum values of the in-phase signal. These signals are used in the error-detecting stage to derive an in-phase offset error signal, a quadrature offset error signal, a phase-error signal, and an amplitude-error signal from which an in-phase-offset-correcting signal, a quadrature-offset-correcting signal, a quadrature phase-correcting signal, and quadrature amplitude-correcting signal are formed by associated controllers.

Abstract: To realize the transfer function in a digital filter circuit:H(z)=b(1-z.sup.-kn)(1-z.sup.-n).sup.m-1 /(1-z.sup.-).sup.m,the following sections are cascaded: a multiplier for multiplying by 2.sup.-q ; m-1 integrators, each including a delay element which provides a delay equal to the period of the input sampling frequency; and mth integrator including a delay element which is reset by the output sampling clock; a sampling device which is switched at the output sampling clock rate; m-2 differentiators, each including a delay element which provides a delay equal to the period of the output sampling clock; and an (m-1)st differentiator including k delay elements which each provide a delay equal to the period of the output sampling clock.

Abstract: A digital demodulator demodulates and separates the individual components of a digitized stereo multiplex signal which contains a narrowband information channel at three times the pilot signal frequency. Demodulation is accomplished by means of five digital demodulators to which respective carriers are applied from a carrier conditoning circuit. Each carrier has a frequency of the pilot signal frequency, twice the pilot signal frequency or three times the pilot signal frequency. The carriers are generated as data word sequences which contain only the values +1, -1 and 0. The sampling interval for the remaining carrier is 60.degree., beginning from 0.degree.. The signal sampling frequencies are adapted to the different sampling frequencies of the carriers by means of decimation circuits. Each of the six components is freed from interfering adjacent signals by a low-pass filter.