Patents by Inventor Werner Robl

Werner Robl has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11276624
    Abstract: A semiconductor device includes: a semiconductor substrate; a power device formed in the semiconductor substrate; a metal bilayer formed over the semiconductor substrate, the metal bilayer including a discontinuous metal layer formed on and in contact with a continuous base metal layer; and one or more contact pads formed in the metal bilayer or in a metallization layer above the metal bilayer. The discontinuous metal layer includes a plurality of metal blocks which are laterally spaced apart from one another and which form a heat sink structure over the power device. The continuous base metal layer is configured to laterally spread heat energy from the power device to the plurality of metal blocks. Methods of producing the semiconductor device are also described.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: March 15, 2022
    Assignee: Infineon Technologies Austria AG
    Inventors: Michael Nelhiebel, Heiko Assmann, Olaf Heitzsch, Jakob Kriz, Sven Lanzerstorfer, Rainer Pelzer, Werner Robl, Bernhard Weidgans, Johannes Zechner
  • Patent number: 11171049
    Abstract: According to various embodiments, a device may include: a semiconductor region; a metallization layer disposed over the semiconductor region; and a self-organizing barrier layer disposed between the metallization layer and the semiconductor region, wherein the self-organizing barrier layer comprises a first metal configured to be self-segregating from the metallization layer.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: November 9, 2021
    Assignee: Infineon Technologies AG
    Inventors: Werner Robl, Michael Fugger, Carsten Schaeffer, Michael Nelhiebel, Klemens Pruegl
  • Publication number: 20210183732
    Abstract: A semiconductor device includes: a semiconductor substrate; a power device formed in the semiconductor substrate; a metal bilayer formed over the semiconductor substrate, the metal bilayer including a discontinuous metal layer formed on and in contact with a continuous base metal layer; and one or more contact pads formed in the metal bilayer or in a metallization layer above the metal bilayer. The discontinuous metal layer includes a plurality of metal blocks which are laterally spaced apart from one another and which form a heat sink structure over the power device. The continuous base metal layer is configured to laterally spread heat energy from the power device to the plurality of metal blocks. Methods of producing the semiconductor device are also described.
    Type: Application
    Filed: December 17, 2019
    Publication date: June 17, 2021
    Inventors: Michael Nelhiebel, Heiko Assmann, Olaf Heitzsch, Jakob Kriz, Sven Lanzerstorfer, Rainer Pelzer, Werner Robl, Bernhard Weidgans, Johannes Zechner
  • Publication number: 20200343094
    Abstract: An electronic device, an electronic module comprising the electronic device and methods for fabricating the same are disclosed. In one example, the electronic device includes a semiconductor substrate and a metal stack disposed on the semiconductor substrate, wherein the metal stack comprises a first layer, wherein the first layer comprises NiSi.
    Type: Application
    Filed: July 10, 2020
    Publication date: October 29, 2020
    Applicant: Infineon Technologies AG
    Inventors: Paul Frank, Gretchen Adema, Thomas Bertaud, Michael Ehmann, Eric Graetz, Kamil Karlovsky, Evelyn Napetschnig, Werner Robl, Tobias Schmidt, Joachim Seifert, Frank Wagner, Stefan Woehlert
  • Patent number: 10741402
    Abstract: An electronic device, an electronic module comprising the electronic device and methods for fabricating the same are disclosed. In one example, the electronic device includes a semiconductor substrate and a metal stack disposed on the semiconductor substrate, wherein the metal stack comprises a first layer, wherein the first layer comprises NiSi.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: August 11, 2020
    Assignee: Infineon Technologies AG
    Inventors: Paul Frank, Gretchen Adema, Thomas Bertaud, Michael Ehmann, Eric Graetz, Kamil Karlovsky, Evelyn Napetschnig, Werner Robl, Tobias Schmidt, Joachim Seifert, Frank Wagner, Stefan Woehlert
  • Patent number: 10648096
    Abstract: An electrolyte may be provided. The electrolyte may include at least one additive configured to decompose or evaporate at a temperature above approximately 100° C., and a water soluble metal salt, and the electrolyte may be free from carbon nanotubes. In various embodiments, a method of forming a metal layer may be provided: The method may include depositing a metal layer on a carrier using an electrolyte, wherein the electrolyte may include at least one additive configured to decompose or evaporate at a temperature above approximately 100° C. and a water soluble metal salt, wherein the electrolyte is free from carbon nanotubes; and annealing the metal layer to form a metal layer comprising a plurality of pores. In various embodiments, a semiconductor device may be provided.
    Type: Grant
    Filed: November 23, 2015
    Date of Patent: May 12, 2020
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Werner Robl, Michael Melzl, Manfred Schneegans, Bernhard Weidgans, Franziska Haering
  • Patent number: 10446469
    Abstract: A semiconductor device includes a base element and a copper element over the base element. The copper element includes a layer stack having at least two copper layers and at least one intermediate conductive layer of a material different from copper. The at least two copper layers and the at least one intermediate conductive layer are alternately stacked over each other.
    Type: Grant
    Filed: July 22, 2016
    Date of Patent: October 15, 2019
    Assignee: Infineon Technologies AG
    Inventors: Thomas Detzel, Johann Gross, Robert Illing, Maximilian Krug, Sven Gustav Lanzerstorfer, Michael Nelhiebel, Werner Robl, Michael Rogalli, Stefan Woehlert
  • Publication number: 20190267283
    Abstract: According to various embodiments, a device may include: a semiconductor region; a metallization layer disposed over the semiconductor region; and a self-organizing barrier layer disposed between the metallization layer and the semiconductor region, wherein the self-organizing barrier layer comprises a first metal configured to be self-segregating from the metallization layer.
    Type: Application
    Filed: May 7, 2019
    Publication date: August 29, 2019
    Inventors: Werner Robl, Michael Fugger, Carsten Schaeffer, Michael Nelhiebel, Klemens Pruegl
  • Publication number: 20190221533
    Abstract: A semiconductor device includes a semiconductor chip, an electrical connection element for electrically connecting the semiconductor device to a carrier, and a metallization adjoining the electrical connection element, the metallization contains porous nanocrystalline copper that contains portions of organic acids.
    Type: Application
    Filed: January 14, 2019
    Publication date: July 18, 2019
    Applicant: Infineon Technologies AG
    Inventors: Horst THEUSS, Rudolf BERGER, Walter HARTNER, Veronika HUBER, Werner ROBL
  • Patent number: 10332793
    Abstract: According to various embodiments, a device may include: a semiconductor region; a metallization layer disposed over the semiconductor region; and a self-organizing barrier layer disposed between the metallization layer and the semiconductor region, wherein the self-organizing barrier layer comprises a first metal configured to be self-segregating from the metallization layer.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: June 25, 2019
    Assignee: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Werner Robl, Michael Fugger, Carsten Schaeffer, Michael Nelhiebel, Klemens Pruegl
  • Publication number: 20180082848
    Abstract: An electronic device, an electronic module comprising the electronic device and methods for fabricating the same are disclosed. In one example, the electronic device includes a semiconductor substrate and a metal stack disposed on the semiconductor substrate, wherein the metal stack comprises a first layer, wherein the first layer comprises NiSi.
    Type: Application
    Filed: August 31, 2017
    Publication date: March 22, 2018
    Applicant: Infineon Technologies AG
    Inventors: Paul Frank, Gretchen Adema, Thomas Bertaud, Michael Ehmann, Eric Graetz, Kamil Karlovsky, Evelyn Napetschnig, Werner Robl, Tobias Schmidt, Joachim Seifert, Frank Wagner, Stefan Woehlert
  • Publication number: 20170154813
    Abstract: According to various embodiments, a device may include: a semiconductor region; a metallization layer disposed over the semiconductor region; and a self-organizing barrier layer disposed between the metallization layer and the semiconductor region, wherein the self-organizing barrier layer comprises a first metal configured to be self-segregating from the metallization layer.
    Type: Application
    Filed: November 30, 2015
    Publication date: June 1, 2017
    Inventors: Werner Robl, Michael Fugger, Carsten Schaeffer, Michael Nelhiebel, Klemens Pruegl
  • Publication number: 20160343662
    Abstract: One or more embodiments relate to a method for making a semiconductor structure, comprising: providing a workpiece; forming a barrier layer over the workpiece; forming a separation layer over the barrier layer; forming a conductive layer over the separation layer; and wet etching the conductive layer.
    Type: Application
    Filed: July 29, 2016
    Publication date: November 24, 2016
    Inventors: Thomas Fischer, Juergen Foerster, Werner Robl, Andreas Stueckjuergen
  • Publication number: 20160329263
    Abstract: A semiconductor device includes a base element and a copper element over the base element. The copper element includes a layer stack having at least two copper layers and at least one intermediate conductive layer of a material different from copper. The at least two copper layers and the at least one intermediate conductive layer are alternately stacked over each other.
    Type: Application
    Filed: July 22, 2016
    Publication date: November 10, 2016
    Inventors: Thomas Detzel, Johann Gross, Robert Illing, Maximilian Krug, Sven Gustav Lanzerstorfer, Michael Nelhiebel, Werner Robl, Michael Rogalli, Stefan Woehlert
  • Patent number: 9425146
    Abstract: One or more embodiments relate to a method for making a semiconductor structure, comprising: providing a workpiece; forming a barrier layer over the workpiece; forming a separation layer over the barrier layer; forming a conductive layer over the separation layer; and wet etching the conductive layer.
    Type: Grant
    Filed: September 28, 2010
    Date of Patent: August 23, 2016
    Assignee: Infineon Technologies AG
    Inventors: Thomas Fischer, Juergen Foerster, Werner Robl, Andreas Stueckjuergen
  • Patent number: 9418937
    Abstract: An integrated circuit includes a base element and a copper element over the base element, the copper element having a thickness of at least 5 ?m and a ratio of average grain size to thickness of less than 0.7.
    Type: Grant
    Filed: December 9, 2011
    Date of Patent: August 16, 2016
    Assignee: Infineon Technologies AG
    Inventors: Thomas Detzel, Johann Gross, Robert Illing, Maximilian Krug, Sven Gustav Lanzerstorfer, Michael Nelhiebel, Werner Robl, Michael Rogalli, Stefan Woehlert
  • Publication number: 20160168739
    Abstract: An electrolyte may be provided. The electrolyte may include at least one additive configured to decompose or evaporate at a temperature above approximately 100° C., and a water soluble metal salt, and the electrolyte may be free from carbon nanotubes. In various embodiments, a method of forming a metal layer may be provided: The method may include depositing a metal layer on a carrier using an electrolyte, wherein the electrolyte may include at least one additive configured to decompose or evaporate at a temperature above approximately 100° C. and a water soluble metal salt, wherein the electrolyte is free from carbon nanotubes; and annealing the metal layer to form a metal layer comprising a plurality of pores. In various embodiments, a semiconductor device may be provided.
    Type: Application
    Filed: November 23, 2015
    Publication date: June 16, 2016
    Inventors: Werner ROBL, Michael MELZL, Manfred SCHNEEGANS, Bernhard WEIDGANS, Franziska HAERING
  • Publication number: 20140242374
    Abstract: Various methods, apparatuses and devices relate to porous metal layers on a substrate which are three-dimensionally coated. In one embodiment, a porous metal layer is deposited over a substrate. The porous metal layer can be three-dimensionally coated with a coating material.
    Type: Application
    Filed: February 22, 2013
    Publication date: August 28, 2014
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Johann Strasser, Thomas Kunstmann, Manfred Frank, Werner Robl, Maximilian Krug, Simon Faiss, Matthias Mueller
  • Patent number: 8786085
    Abstract: One or more embodiments relate to a semiconductor structure, comprising: a barrier layer overlying a workpiece surface; a seed layer overlying the barrier layer; an inhibitor layer overlying said seed layer, the inhibitor layer having a opening exposing a portion of the seed layer, and a fill layer overlying the exposed portion of the seed layer.
    Type: Grant
    Filed: November 8, 2012
    Date of Patent: July 22, 2014
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Barth, Mathias Vaupel, Rainer Steiner, Werner Robl, Jens Pohl, Joern Plagmann, Gottfried Beer
  • Patent number: 8759207
    Abstract: One or more embodiments relate to a method of forming a semiconductor structure, comprising: providing a workpiece; forming a barrier layer over the workpiece; forming a seed layer over the barrier layer; forming an inhibitor layer over the seed layer; removing a portion of said inhibitor layer to expose a portion of the seed layer; and selectively depositing a fill layer on the exposed seed layer.
    Type: Grant
    Filed: November 8, 2012
    Date of Patent: June 24, 2014
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Barth, Mathias Vaupel, Rainer Steiner, Werner Robl, Jens Pohl, Joem Plagmann, Gottfried Beer