Abstract: A synchronizing unit generates synchronized pulse sequences from an external digital signal pulse sequence, with the assistance of an internal work clock, using two serially connected flip-flops for accepting external digital signal pulse sequences and for providing synchronized data and clock pulses corresponding thereto. The clock of the external digital signal pulse sequence has the same clock frequency as the work clock with which the data is to be synchronized, but with an undefined phase relation. For the purpose of synchronizing, during a acquisition state, a switching stage is driven into a first state by the clock of the external digital signal pulse sequence, and a divider is triggered by the output of the switching stage. In a second state of the switching stage, corresponding to a normal operating state, the first switching stage is deactivated and the divider operates continuously.

Abstract: At least two operating statuses selected by a selection signal are respectively controlled by connecting an individual clock signal sequence. A change of the selection signal initially remains ineffective until the next clock edge of a defined direction has appeared in the previously selected clock signal sequence. The clock signal status which has thus appeared is maintained until the next clock edge of the same direction has appeared in the clock signal sequence allocated to the operating status to be activated. This clock signal sequence is now connected through to the clock-controlled device. This type of delayed switching results in complete clock periods in the connected through clock signal, even given changes in the selection signal which occur asynchronously thereto.