Abstract: A first SOI field effect transistor with predetermined transistor properties, comprising: a laterally delimited layer sequence with a gate-insulating layer and a gate region on an undoped substrate; a spacer layer having a predetermined thickness on at least a portion of the sidewalls of the laterally delimited layer sequence; and two source/drain regions in two surface regions of the substrate which are adjoined by the spacer layer, with a predetermined dopant concentration profile, the layer sequence and the spacer layer forming a shading structure that prevents dopant from being introduced into a surface region of the substrate between the two source/drain regions during the production of the first SOI field effect transistor, wherein the predetermined transistor properties of the first SOI field effect transistor are set by setting the thickness of the spacer layer and by the dopant concentration profile.

Abstract: Method for producing a first SOI field effect transistor with predetermined transistor properties by forming a laterally delimited layer sequence with a gate-insulating layer and a gate region on an undoped substrate, forming a spacer layer having a predetermined thickness, on at least a portion of the sidewalls of the laterally delimited layer sequence, and forming two source/drain regions having a predetermined dopant concentration profile, by introducing dopant into two surface regions of the substrate which are adjoined by the spacer layer, the layer sequence and the spacer layer forming a shading structure that prevents dopant from being introduced into a surface region of the substrate between the two source/drain regions, wherein the predetermined transistor properties of the first SOI field effect transistor are set by setting the thickness of the spacer layer and by setting the dopant concentration profile.

Abstract: An arrangement and process for producing a circuit arrangement is disclosed. The process includes having a layer arrangement, in which two electrically conductive interconnects running substantially parallel to one another are formed on a substrate. At least one auxiliary structure is formed on the substrate and between the two interconnects, running in a first direction, which first direction includes an angle of between 45 degrees and 90 degrees with a connecting axis of the interconnects, running orthogonally with respect to the two interconnects, the at least one auxiliary structure being produced from a material which allows the at least one auxiliary structure to be selectively removed from a dielectric layer. The dielectric layer is formed between the two interconnects, in such a manner that the at least one auxiliary structure is at least partially covered by the dielectric layer.

Abstract: In order to fabricate a semiconductor memory, a trench capacitor is arranged in a first trench. Beside the first trench, a first longitudinal trench and, parallel on the other side of the first trench, a second longitudinal trench are arranged in the substrate. A first spacer word line is arranged in the first longitudinal trench and a second spacer word line is arranged in the second longitudinal trench. There are arranged in the first trench connecting webs between the first spacer word line and the second spacer word line which have a thickness which, in the direction of the first spacer word line, is less than half the width of the first trench in the direction of the first spacer word line.

Abstract: An arrangement and process for producing a circuit arrangement is disclosed. The process includes having a layer arrangement, in which two electrically conductive interconnects running substantially parallel to one another are formed on a substrate. At least one auxiliary structure is formed on the substrate and between the two interconnects, running in a first direction, which first direction includes an angle of between 45 degrees and 90 degrees with a connecting axis of the interconnects, running orthogonally with respect to the two interconnects, the at least one auxiliary structure being produced from a material which allows the at least one auxiliary structure to be selectively removed from a dielectric layer. The dielectric layer is formed between the two interconnects, in such a manner that the at least one auxiliary structure is at least partially covered by the dielectric layer.

Abstract: Method for producing a first SOI field effect transistor with predetermined transistor properties by forming a laterally delimited layer sequence with a gate-insulating layer and a gate region on an undoped substrate, forming a spacer layer having a predetermined thickness, on at least a portion of the sidewalls of the laterally delimited layer sequence, and forming two source/drain regions having a predetermined dopant concentration profile, by introducing dopant into two surface regions of the substrate which are adjoined by the spacer layer, the layer sequence and the spacer layer forming a shading structure that prevents dopant from being introduced into a surface region of the substrate between the two source/drain regions, wherein the predetermined transistor properties of the first SOI field effect transistor are set by setting the thickness of the spacer layer and by setting the dopant concentration profile.

Abstract: In order to fabricate a semiconductor memory, a trench capacitor is arranged in a first trench. Beside the first trench, a first longitudinal trench and, parallel on the other side of the first trench, a second longitudinal trench are arranged in the substrate. A first spacer word line is arranged in the first longitudinal trench and a second spacer word line is arranged in the second longitudinal trench. There are arranged in the first trench connecting webs between the first spacer word line and the second spacer word line which have a thickness which, in the direction of the first spacer word line, is less than half the width of the first trench in the direction of the first spacer word line.

Abstract: Buried straps are produced on one side in deep trench structures. A PVD process is used to deposit masking material in the recess inclined at an angle. As a result, a masking wedge is produced on the buried strap, on one side in the base region of the recess. The masking wedge serves as a mask during a subsequent anisotropic etching step, which is carried out selectively with respect to the masking wedge, for removing the buried strap on one side.

Abstract: Buried straps are produced on one side in deep trench structures. A PVD process is used to deposit masking material in the recess inclined at an angle. As a result, a masking wedge is produced on the buried strap, on one side in the base region of the recess. The masking wedge serves as a mask during a subsequent anisotropic etching step, which is carried out selectively with respect to the masking wedge, for removing the buried strap on one side.