Abstract: A semiconductor neuron has input electrodes are coupled capacitively to a floating gate (FG) whose potential controls the current of a MOS field effect transistor (NT). A respective neuron input (E1 . . . E4) can be connected to partial electrodes (1 . . . 7) of a respective input electrode in such a way that the total surface area of the partial electrodes connected to the respective neuron input corresponds to a respective weight of the neuron input. This results in high processing speed of a hardware neuron with the flexibility of a software neuron.

Abstract: In the read amplifier a mismatch of the inception voltages of cross-coupled transistors (M5, M6) of the read amplifier are compensated by four further transistors (M1 . . . M4), whereby a defined equalizing of the bitlines advantageously takes place with these further transistors simultaneously in what is called the equalize phase. The compensation takes place in that the bitline that is connected with the transistor with the lower inception voltage is charged to a higher level in the pre-load phase. This higher bitline level is switched to the gate of the transistor connected with the other bitline. In the evaluation phase the transistor with the higher inception voltage becomes more strongly conductive. Read amplifiers of this sort are most significant for memory generations beginning at 1 Gbit, since the mismatch due to the variation of the input voltages of the transistors can no longer usefully be solved by a correspondingly large gate surface of the cross-coupled transistors in the read amplifier.

Abstract: The circuit arrangement compares a quantity supplied by a first neuron MOS field effect transistor (M1) to a reference quantity that is made available by a reference source (R). A current mirror (SP) is provided therefor, this enabling a comparison of a second current (I.sub.2) supplied by a reference transistor (R) to a first current (I.sub.1) supplied by the first neuron MOS field effect transistor (M1). The evaluator circuit is activated or, respectively, decoupled by a first switch unit (S1) and a second switch unit (S2). What is thereby achieved is that no current flows in the evaluator circuit in the quiescent condition. The comparison result is applied to an inverter unit (IS). Since the inverter unit (IS) is decoupled from the evaluator circuit by the first switch unit (S1), an undefined level is never adjacent at the output (AIS) of the inverter unit (IS). This can be advantageously utilized in the further data processing in following stages.

Abstract: In a circuit arrangement wherein all logic elements can be represented in the form of a threshold value equation, for this purpose, transistors connected in parallel of a transistor unit are dimensioned in such a way that the cross-currents flowing through the transistors respectively represent a weighted summand of a first term of the threshold value equation. A second term of the threshold value equation is formed by a reference current representing the second term value. An evaluation unit compares an overall current, which results from the sum of cross-currents, with the reference current. The evaluation result is present at an output of the evaluation unit in the form of a stable output signal.

Abstract: A threshold logic circuit with a low space requirement includes a first and at least one second circuit portion, each of which has an evaluator circuit and at least two branches to be evaluated. A partial sum signal formed in the first circuit portion is jointly used for the at least one second circuit portion and is not formed separately in each case. The main advantage is a low chip area consumption.

Abstract: A method and apparatus for the reversible contacting of a semiconductor circuit level to assist in performing a function test. The apparatus includes a testing head having test points arranged at a test side lying opposite the contact surfaces of a semiconductor circuit level. The test points are formed of liquid contacts in recesses in the test side of the testing head wherein the liquid contacts form menisci that project beyond the surface of the testing head. The recesses, in turn, are provided for metallizations which are connected to electrically-conductive leads. In addition, the surface may be provided with a roughening or with etched trenches.

Abstract: A defined zero point voltage (V.sub.0), dependent on a settable zero point voltage target value (V.sub.0,soll), is enabled in amplifier stages (1 . . . k) with neuron MOS transistors (T10,1 . . . T10,k). This is generally required because, for example, due to a process-caused charging of the floating gates of the neuron MOS transistors, and due to a capacitively coupled-in voltage from the channel region, an undefined zero point displacement of the transmission characteristic curve results. The devices can be used together with the amplifier stages, e.g. in video and audio technology, in sensor technology, in analog computers, in fuzzy circuits and in neural networks.

Abstract: Amplifier circuits having at least one neuron MOS transistor in which a coupling gate is connected to an amplifier output and at least one further coupling gate is connected with a respective amplifier input are provided. The amplifier circuit exhibits a linear transmission behavior even in large-signal operation and can be constructed using relatively few components. Furthermore, the gain is easy to set.

Abstract: A terminal metallization (8) is applied onto and structured on a layer structure on the upper side of the component, the terminal metallization is applied on the upper side of an insulating layer (7) with an opening on a metallization (6) provided for electrical connection. By filling a hole produced in a covering dielectric with metal, a contact rod (12) seated on this terminal metallization (8) is formed. This contact rod is resiliently movable in a surrounding opening (14) of the component on the free part of the terminal metallization (8) anchored in the layer structure. This enables the reversible contacting of the component to a further component arranged vertically thereto, whereby the planar upper sides lying opposite one another can be brought into intimate contact because the contact rod (12) pressed against a contact (15) of the other component is pressed back into the opening (14) and an adequately firm connection of the contacts is achieved by the spring power of the terminal metallization (8).

Abstract: A processing circuit has a computing cycle divided into several subcycles of uniform duration. The time base values of the last three nulls of a square wave signal produced from the sinusoidal signal of a wheel speed sensor are stored in a register with three places. At the beginning of a subcycle the difference D of the latest and of the oldest time base values stored in the register is formed and in some cases after limiting is converted to a value 1/D and stored, while the previously stored oldest value is erased. At the start of a new computing cycle the stored value 1/D is further processed as the new wheel speed.

Abstract: A processing circuit has a computing cycle divided into several subcycles of uniform duration. The time base values of the last three nulls of a square wave signal produced from the sinusoidal signal of a wheel speed sensor are stored in a register with three places. At the beginning of a subcycle the difference D of the latest and of the oldest time base values stored in the register is formed and in some cases after limiting is converted to a value 1/D and stored, while the previously stored oldest value is erased. At the start of a new computing cycle the stored value 1/D is further processed as the new wheel speed.

Abstract: In an arrangement for signal transmission between chip layers of a vertically integrated circuit, a defined, capacitive signal transmission ensues between a part of the vertically integrated circuit in one chip layer and a further part of the vertically integrated circuit in a further chip layer by means of a coupling capacitance. Particularly given high connection densities, a large number of freely placeable and reliable vertical signal connections can be produced directly from the inside of one chip layer to the inside of a neighboring chip layer without extremely high demands being made on the adjustment of the chip layers relative to one another and on the surface planarity of the individual chip layers.

Abstract: An electronic device includes an acceleration-sensitive sensor, an electronic circuit arrangement for analyzing the output signal from the sensor, an ignition output element, an ignition element, and a safety device for the vehicle's occupants. To test the operating readiness of the ignition element, an oscillator circuit is also provided, which applies an output signal to the ignition element. The resulting voltage drop obtained across the ignition element is compared by means of a window comparator to threshold values.

Abstract: A device for tensioning printing formes (or "printing plates") on a forme (or "plate") cylinder of a rotary printing machine, including a stretching shaft extending through a gap formed in the cylinder, the stretching shaft holding receiving elements and, opposite thereof, clamping surfaces gripping the trailing end of a printing plate, with individual tensioning elements being mounted side by side on the stretching shaft, and the stretching shaft being stretchable, via adjusting elements, linearly in axial direction in order to optimally tension the trailing end of the printing plate independently of a possible stretching of the printing plate.

Abstract: In an arrangement for signal transmission between chip layers of a vertically integrated circuit, a defined, inductive signal transmission ensues between a part of the vertically integrated circuit in one chip layer and a further part of the vertically integrated circuit in a further chip layer by means of a coupling inductance formed by respective coils in the two layers. Particularly given high connection densities, a large number of freely placeable and reliable vertical signal connections can be produced directly from the inside of one chip layer to the inside of a neighboring chip layer without extremely high demands being made on the adjustment of the chip layers relative to one another and on the surface planarity of the individual chip layers.

Abstract: A positioning device for a rubber-blanket cylinder which is supported in double-excentric bearing rings allows a positional adjustment of the rubber-blanket cylinder relative to a plate cylinder and a printing substrate supported on an impression cylinder. The plate cylinder and the impression cylinder have stationary axes of rotation relative to the frame of the printing unit. A printing gap is adjusted by the positioning device to varying printing substrate thickness, and in one terminal position, the rubber-blanket cylinder is fully disengaged from the other cylinders. The rubber-blanket cylinder is shifted along a positioning path with one segment following an arc of a circle which is concentric with the plate cylinder. The parameters of the bearing and the adjusting devices are defined such that the positioning path is traversed while the respective inner and outer bearing rings rotate continuously.

Abstract: A package for receiving articles in successive arrangement and being of a type having one surface provided with projections, includes an outer enclosure defining an interior; and an insert receiving the articles and being placed in the outer enclosure. The insert has at least one inside surface which is provided with an elevation protruding inwardly from the inside surface into the interior of the enclosure, with the projections of the articles engaging in an area between an inner wall and the projection of the insert.

Abstract: In an electronic safety device for vehicle occupants including an acceleration-sensitive sensor, a control unit, and a plurality of inertial restraining devices with associated output stages, a reliable operating mode is guaranteed for the safety device by storing characteristic fault conditions, together with control strategies compensating for these fault conditions. In the event of a fault, the safety device applies the respective, assigned control strategy to activate the restraining devices.

Abstract: A function test is implemented for an individual circuit level (1) that is provided for vertical integration in a semiconductor component. Stacks of circuit levels respectively provided over or under this circuit level in the finished component are simulated as test heads (2, 3). These test heads are provided with terminal contacts for reversible contacting. The circuit level (1) under test is connected to these test heads (2, 3) during the function test, and the test heads are removed after the test.

Abstract: Clamping device for fastening a flexible printing form on a jacket surface of a cylinder includes a structure defining a groove formed in and across a jacket surface of a cylinder for receiving a leading end of a printing form therein, a structure defining a cylinder gap formed axially parallel in the jacket surface of the cylinder for receiving therein a trailing end of the printing form bent with an obtuse angle, a turnable clamping shaft disposed axially parallel in the cylinder and having at least one resilient element fastened thereto, the one resilient element being movable with respect to the trailing end of the printing form, the structure defining the cylinder gap including a leading lateral surface formed in the cylinder and provided with an edge engageable by the trailing end of the printing form, the one resilient element having two legs, one of which, in an unclamped condition of the clamping device, extends freely into the gap.