Abstract: Linear sample and hold phase detectors are disclosed herein. An example phase detector is coupled to an input data signal and a recovered clock signal and includes a linear phase difference generator circuit and a sample and hold circuit. The linear phase difference generator includes a first input coupled to the input data signal and a second input coupled to the recovered clock signal and outputs a first phase difference signal indicative of the phase difference between the input data signal and the recovered clock signal relative to a rising edge of the input data signal and a second phase difference signal indicative of the phase difference between the input data signal and the recovered clock signal relative to a falling edge of the input data signal.

Abstract: In accordance with the teachings described herein, systems and methods are provided for a precision adaptive equalizer. A variable gain equalizer may be used to apply a variable gain to an input signal to generate an equalized output signal. A phase and pattern detector circuit may be coupled in a feedback loop with the variable gain equalizer. The phase and pattern detector circuit may be used to identify a high frequency data pattern in the equalized output signal and compare the high frequency data pattern with a clock signal to detect a high frequency phase error. The phase and pattern detector circuit may be further operable to generate an automatic gain control signal as a function of the high frequency phase error, the automatic gain control signal being fed back to the variable gain equalizer to control the variable gain applied to the input signal.

Abstract: Linear sample and hold phase detectors are disclosed herein. An example phase detector is coupled to an input data signal and a recovered clock signal and includes a linear phase difference generator circuit and a sample and hold circuit. The linear phase difference generator includes a first input coupled to the input data signal and a second input coupled to the recovered clock signal and outputs a first phase difference signal indicative of the phase difference between the input data signal and the recovered clock signal relative to a rising edge of the input data signal and a second phase difference signal indicative of the phase difference between the input data signal and the recovered clock signal relative to a falling edge of the input data signal.

Abstract: In accordance with the teachings described herein, systems and methods are provided for automatically correcting duty cycle distortion. A slicer may be used to receive a data input signal and compare the data input signal with a slicer offset voltage to generate a sliced data signal. The slicer may also receive an offset control signal to automatically adjust the slicer offset voltage. A phase detector may be used to receive the sliced data signal and a recovered clock signal and to compare the sliced data signal with the recovered clock signal to generate a rising edge output signal and a falling edge output signal. The rising edge output signal may correspond to a phase difference between a rising edge of the sliced data signal and an edge of the recovered clock signal. The falling edge output signal may correspond to a phase difference between a falling edge of the sliced data signal and an edge of the recovered clock signal.

Abstract: An adaptive lock position circuit includes a jitter distribution extremity detector and a phase shifting circuit. The jitter distribution extremity detector receives an input data signal and is operable to compare the input data signal with one or more clock signals derived from a recovered clock signal from a clock and data recovery (CDR) circuit to generate one or more control signals that define the boundaries of a jitter extremity detection window. The phase shifting circuit is coupled in a feedback loop with the jitter distribution extremity detector and receives the one or more control signals from the jitter distribution extremity detector and also receives the recovered clock signal. The phase shifting circuit is operable to shift the phase of the recovered clock signal as a function of the one or more control signals to generate a retiming clock signal such that an edge of the retiming clock signal is interpolated within the jitter extremity detection window.

Abstract: A system for dynamically trimming a voltage controlled oscillator operable to receive a trim signal for adjusting a voltage-to-frequency operating characteristic of the voltage controlled oscillator and receive a tune signal to generate an output signal having an output frequency determined by the voltage-to-frequency operating characteristic includes a trim circuit operable to receive the tune signal and generate the trim signal and increment or decrement the trim signal and condition a change in the trim signal during the increment or decrement so that the voltage-to-frequency operating characteristic of the voltage controlled oscillator drifts from a first voltage-to-frequency operating characteristic to a second voltage-to-frequency operating characteristic.

Abstract: A system for dynamically trimming a voltage controlled oscillator operable to receive a trim signal for adjusting a voltage-to-frequency operating characteristic of the voltage controlled oscillator and receive a tune signal to generate an output signal having an output frequency determined by the voltage-to-frequency operating characteristic includes a trim circuit operable to receive the tune signal and generate the trim signal and increment or decrement the trim signal and condition a change in the trim signal during the increment or decrement so that the voltage-to-frequency operating characteristic of the voltage controlled oscillator drifts from a first voltage-to-frequency operating characteristic to a second voltage-to-frequency operating characteristic.