Abstract: A process automatically generating topology data for fabricating large scale integrated circuits. Technology data, a logic function description and logic circuit components are generated and input to a data processing system together with geometric dimension data descriptive of the basic elements of the logic circuit components. The geometric dimension data is assembled into a plurality of intermediate level geometric topology patterns under control of the logic function description and the intermediate level geometric topology patterns are assembled into a prime level geometric topology representative of the logic function description. The logic circuit components are merged with the prime level geometric topology to produce a grid array to be fabricated into a large scale integrated circuit.