Abstract: Extended, alternate and/or modified instruction behavior can be established using a program construct that appears outside a bounded block of program code in such a way that the behavioral changes are limited to the bounded block and coincide with a particular point in the execution thereof. These extensions, alternations and/or modifications are supported in some processor embodiments in ways that add neither additional code space nor additional execution cycles to the bounded block. In general, the particular point in execution of the bounded block may be specified in a variety of ways, including positionally or temporally. Techniques described herein have broad applicability, but will be understood by persons of ordinary skill in the art in the context of certain illustrative code blocks, including zero- (or low-) overhead loops, lightweight procedures and very long instruction word (VLIW) type instruction packets, and processors that support them.

Abstract: A context controller for managing multitasking in a processor and a method of operating the same. In one embodiment, the context controller includes: (1) an event recorder that records occurrences of predetermined events and (2) an event acknowledger, associated with the event recorder, that acknowledges ones of the events based on an identity of a currently-active context.

Abstract: A context controller for managing multitasking in a processor and a method of operating the same. In one embodiment, the context controller includes: (1) a time slice instruction counter that counts a number of instructions executed with respect to a given background task and (2) a background task controller that cyclicly executes a context corresponding to another background task when the number of instructions executed equals a dynamically-programmable time slice value.

Abstract: A communications system including a scheduling entity and a transceiver coupled across a variable timing interface. The scheduling entity forwards frames for transmission and identifies selected frames as persistent. The transceiver includes a queue, a frame manager and a transmission scheduler. The frame manager receives and enqueues forwarded frames and the transmission scheduler dequeues and transmits frames from the queue and forwards persistent frames back to the frame manager. The transmission scheduler includes persistence logic that detects a persistent mark and asserts a persistent signal that is detected by the transmission scheduler. The scheduling entity identifies a persistent frame by setting a bit in a transmit control field of the frame descriptor. The scheduling entity sends a clear persistence command to the transceiver to clear a persistent mark of an identified frame. The transceiver may be configured for wireless communications.

Abstract: A context controller for managing multitasking in a processor and a method of operating the same. In one embodiment, the context controller includes: (1) foreground and background task controllers that allocate processor resources to active contexts corresponding to foreground and background tasks, respectively, and (2) mode switching circuitry, coupled to the foreground and background task controllers, that places the processor in an idle state and a power saving mode when all of the contexts are inactive.

Abstract: A context controller for managing multitasking in a processor and a method of operating the same. In one embodiment, the context controller includes: (1) memory that contains contexts corresponding to background tasks to be executed in the processor, the contexts having status indicators associated therewith and (2) a background task controller that reads the status indicators associated with the contexts and cyclicly activates the contexts based on the status indicators.

Abstract: A context controller for managing multitasking in a processor and a method of operating the same. In one embodiment, the context controller includes: (1) an event recorder that records occurrences of events and (2) an encoder, associated with the event recorder, that, in response to a software instruction, priority encodes bits corresponding to at least some of the events to generate therefrom an event-dependent vector to allow the processor to branch as a function thereof. Vectoring is per-instance of the vector decode software instruction, not per-event or per-context.