Patents by Inventor Wesley H. Morris
Wesley H. Morris has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9201726Abstract: An example integrated circuit includes a first memory array including a first plurality of data groups, each such data group including a respective plurality of data bits. The integrated circuit also includes a first error detection and correction (EDAC) circuit configured to detect and correct an error in a data group read from the first memory array. The integrated circuit also includes a first scrub circuit configured to access in a sequence each of the first plurality of data groups to correct any detected errors therein. Both the first EDAC circuit and the first scrub circuit include spatially redundant circuitry. The first EDAC circuit and the first scrub circuit may include buried guard ring (BGR) structures, and may include parasitic isolation device (PID) structures. The spatially redundant circuitry may include dual interlocked storage cell (DICE) circuits, and may include temporal filtering circuitry.Type: GrantFiled: March 2, 2015Date of Patent: December 1, 2015Assignee: SILICON SPACE TECHNOLOGY CORPORATIONInventors: Wesley H. Morris, David R. Gifford, Rex E. Lowther
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Publication number: 20150169400Abstract: An example integrated circuit includes a first memory array including a first plurality of data groups, each such data group including a respective plurality of data bits. The integrated circuit also includes a first error detection and correction (EDAC) circuit configured to detect and correct an error in a data group read from the first memory array. The integrated circuit also includes a first scrub circuit configured to access in a sequence each of the first plurality of data groups to correct any detected errors therein. Both the first EDAC circuit and the first scrub circuit include spatially redundant circuitry. The first EDAC circuit and the first scrub circuit may include buried guard ring (BGR) structures, and may include parasitic isolation device (PID) structures. The spatially redundant circuitry may include dual interlocked storage cell (DICE) circuits, and may include temporal filtering circuitry.Type: ApplicationFiled: March 2, 2015Publication date: June 18, 2015Inventors: WESLEY H. MORRIS, DAVID R. GIFFORD, REX E. LOWTHER
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Patent number: 8972819Abstract: An example integrated circuit includes a first memory array including a first plurality of data groups, each such data group including a respective plurality of data bits. The integrated circuit also includes a first error detection and correction (EDAC) circuit configured to detect and correct an error in a data group read from the first memory array. The integrated circuit also includes a first scrub circuit configured to access in a sequence each of the first plurality of data groups to correct any detected errors therein. Both the first EDAC circuit and the first scrub circuit include spatially redundant circuitry. The first EDAC circuit and the first scrub circuit may include buried guard ring (BGR) structures, and may include parasitic isolation device (PID) structures. The spatially redundant circuitry may include dual interlocked storage cell (DICE) circuits, and may include temporal filtering circuitry.Type: GrantFiled: November 21, 2012Date of Patent: March 3, 2015Assignee: Silicon Space Technology CorporationInventors: Wesley H. Morris, David R. Gifford, Rex E. Lowther
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Patent number: 8729640Abstract: Semiconductor devices can be fabricated using conventional designs and process but including specialized structures to reduce or eliminate detrimental effects caused by various forms of radiation. Such semiconductor devices can include the one or more parasitic isolation devices and/or buried guard ring structures disclosed in the present application. The introduction of design and/or process steps to accommodate these novel structures is compatible with conventional CMOS fabrication processes, and can therefore be accomplished at relatively low cost and with relative simplicity.Type: GrantFiled: July 29, 2013Date of Patent: May 20, 2014Assignee: Silicon Space Technology CorporationInventor: Wesley H. Morris
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Publication number: 20130313620Abstract: Semiconductor devices can be fabricated using conventional designs and process but including specialized structures to reduce or eliminate detrimental effects caused by various forms of radiation. Such semiconductor devices can include the one or more parasitic isolation devices and/or buried guard ring structures disclosed in the present application. The introduction of design and/or process steps to accommodate these novel structures is compatible with conventional CMOS fabrication processes, and can therefore be accomplished at relatively low cost and with relative simplicity.Type: ApplicationFiled: July 29, 2013Publication date: November 28, 2013Applicant: SILICON SPACE TECHNOLOGY CORPORATIONInventor: WESLEY H. MORRIS
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Patent number: 8497195Abstract: Semiconductor devices can be fabricated using conventional designs and process but including specialized structures to reduce or eliminate detrimental effects caused by various forms of radiation. Such semiconductor devices can include the one or more parasitic isolation devices and/or buried guard ring structures disclosed in the present application. The introduction of design and/or process steps to accommodate these novel structures is compatible with conventional CMOS fabrication processes, and can therefore be accomplished at relatively low cost and with relative simplicity.Type: GrantFiled: January 9, 2012Date of Patent: July 30, 2013Assignee: Silicon Space Technology CorporationInventor: Wesley H. Morris
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Publication number: 20130166990Abstract: An example integrated circuit includes a first memory array including a first plurality of data groups, each such data group including a respective plurality of data bits. The integrated circuit also includes a first error detection and correction (EDAC) circuit configured to detect and correct an error in a data group read from the first memory array. The integrated circuit also includes a first scrub circuit configured to access in a sequence each of the first plurality of data groups to correct any detected errors therein. Both the first EDAC circuit and the first scrub circuit include spatially redundant circuitry. The first EDAC circuit and the first scrub circuit may include buried guard ring (BGR) structures, and may include parasitic isolation device (PID) structures. The spatially redundant circuitry may include dual interlocked storage cell (DICE) circuits, and may include temporal filtering circuitry.Type: ApplicationFiled: November 21, 2012Publication date: June 27, 2013Inventors: Wesley H. Morris, David R. Gifford, Rex E. Lowther
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Publication number: 20130059421Abstract: Semiconductor devices can be fabricated using conventional designs and process but including specialized structures to reduce or eliminate detrimental effects caused by various forms of radiation. Such semiconductor devices can include one or more parasitic isolation devices and/or buried layer structures disclosed in the present application. The introduction of design and/or process steps to accommodate these novel structures is compatible with conventional CMOS fabrication processes, and can therefore be accomplished at relatively low cost and with relative simplicity.Type: ApplicationFiled: September 27, 2012Publication date: March 7, 2013Inventor: Wesley H. Morris
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Patent number: 8278719Abstract: Semiconductor devices can be fabricated using conventional designs and process but including specialized structures to reduce or eliminate detrimental effects caused by various forms of radiation. Such semiconductor devices can include one or more parasitic isolation devices and/or buried layer structures disclosed in the present application. The introduction of design and/or process steps to accommodate these novel structures is compatible with conventional CMOS fabrication processes, and can therefore be accomplished at relatively low cost and with relative simplicity.Type: GrantFiled: October 16, 2006Date of Patent: October 2, 2012Assignee: Silicon Space Technology Corp.Inventor: Wesley H. Morris
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Patent number: 8252642Abstract: Semiconductor devices can be fabricated using conventional designs and process but including specialized structures to reduce or eliminate detrimental effects caused by various forms of radiation. Such semiconductor devices can include one or more parasitic isolation devices and/or buried layer structures disclosed in the present application. The introduction of design and/or process steps to accommodate these novel structures is compatible with conventional CMOS fabrication processes, and can therefore be accomplished at relatively low cost and with relative simplicity.Type: GrantFiled: November 30, 2009Date of Patent: August 28, 2012Assignee: Silicon Space Technology Corp.Inventor: Wesley H. Morris
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Publication number: 20120108045Abstract: Semiconductor devices can be fabricated using conventional designs and process but including specialized structures to reduce or eliminate detrimental effects caused by various forms of radiation. Such semiconductor devices can include the one or more parasitic isolation devices and/or buried guard ring structures disclosed in the present application. The introduction of design and/or process steps to accommodate these novel structures is compatible with conventional CMOS fabrication processes, and can therefore be accomplished at relatively low cost and with relative simplicity.Type: ApplicationFiled: January 9, 2012Publication date: May 3, 2012Inventor: Wesley H. Morris
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Patent number: 8093145Abstract: Semiconductor devices can be fabricated using conventional designs and process but including specialized structures to reduce or eliminate detrimental effects caused by various forms of radiation. Such semiconductor devices can include the one or more parasitic isolation devices and/or buried guard ring structures disclosed in the present application. The introduction of design and/or process steps to accommodate these novel structures is compatible with conventional CMOS fabrication processes, and can therefore be accomplished at relatively low cost and with relative simplicity.Type: GrantFiled: December 3, 2007Date of Patent: January 10, 2012Assignee: Silicon Space Technology Corp.Inventor: Wesley H. Morris
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Publication number: 20100267212Abstract: Semiconductor devices can be fabricated using conventional designs and process but including specialized structures to reduce or eliminate detrimental effects caused by various forms of radiation. Such semiconductor devices can include one or more parasitic isolation devices and/or buried layer structures disclosed in the present application. The introduction of design and/or process steps to accommodate these novel structures is compatible with conventional CMOS fabrication processes, and can therefore be accomplished at relatively low cost and with relative simplicity.Type: ApplicationFiled: November 30, 2009Publication date: October 21, 2010Inventor: Wesley H. Morris
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Patent number: 7804138Abstract: Semiconductor devices can be fabricated using conventional designs and process but including specialized structures to reduce or eliminate detrimental effects caused by various forms of radiation. Such semiconductor devices can include the one or more parasitic isolation devices and/or buried guard ring structures disclosed in the present application. The introduction of design and/or process steps to accommodate these novel structures is compatible with conventional CMOS fabrication processes, and can therefore be accomplished at relatively low cost and with relative simplicity.Type: GrantFiled: July 13, 2006Date of Patent: September 28, 2010Assignee: Silicon Space Technology Corp.Inventor: Wesley H. Morris
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Patent number: 7629654Abstract: Semiconductor devices can be fabricated using conventional designs and process but including specialized structures to reduce or eliminate detrimental effects caused by various forms of radiation. Such semiconductor devices can include the one or more parasitic isolation devices and/or buried guard ring structures disclosed in the present application. The introduction of design and/or process steps to accommodate these novel structures is compatible with conventional CMOS fabrication processes, and can therefore be accomplished at relatively low cost and with relative simplicity.Type: GrantFiled: December 3, 2007Date of Patent: December 8, 2009Assignee: Silicon Space Technology Corp.Inventor: Wesley H. Morris
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Publication number: 20080188045Abstract: Semiconductor devices can be fabricated using conventional designs and process but including specialized structures to reduce or eliminate detrimental effects caused by various forms of radiation. Such semiconductor devices can include the one or more parasitic isolation devices and/or buried guard ring structures disclosed in the present application. The introduction of design and/or process steps to accommodate these novel structures is compatible with conventional CMOS fabrication processes, and can therefore be accomplished at relatively low cost and with relative simplicity.Type: ApplicationFiled: December 3, 2007Publication date: August 7, 2008Inventor: Wesley H. Morris
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Publication number: 20080142899Abstract: Radiation hardened integrated circuit devices may be fabricated using conventional designs and process, but including specialized structures to reduce or eliminate detrimental effects caused by various forms of radiation. An exemplary BGR structure includes a high-dose buried guard ring (HBGR) layer which is contacted to ground through the backside of the wafer or circuit die, thus forming a Backside BGR (BBGR) structure. In certain embodiments, the starting wafer may be highly doped to reduce the resistance from the HBGR to the back of the wafer, which is then further contacted to ground through the package. The performance of such devices may be further improved by using an electrically conductive adhesive to attach the die and to electrically connect the silicon substrate region to the package's conductive header, substrate, or die attach pad, which in turn is typically connected to one or more package pins/balls.Type: ApplicationFiled: August 4, 2007Publication date: June 19, 2008Applicant: SILICON SPACE TECHNOLOGY CORPORATIONInventors: Wesley H. Morris, Jon Gwin, Rex Lowther
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Patent number: 7304354Abstract: Semiconductor devices can be fabricated using conventional designs and process but including specialized structures to reduce or eliminate detrimental effects caused by various forms of radiation. Such semiconductor devices can include the one or more parasitic isolation devices and/or buried guard ring structures disclosed in the present application. The introduction of design and/or process steps to accommodate these novel structures is compatible with conventional CMOS fabrication processes, and can therefore be accomplished at relatively low cost and with relative simplicity.Type: GrantFiled: September 27, 2004Date of Patent: December 4, 2007Assignee: Silicon Space Technology Corp.Inventor: Wesley H. Morris
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Patent number: 4662059Abstract: A MOS/SOI field-effect transistor is made by applying a layer of a photoresist over the surface of a single-crystalline silicon layer which is on a substrate of an insulating material, such as sapphire. The surface of the silicon layer is along a (100) crystallographic plane. The photoresist layer is defined to provide an area of the photoresist layer over the area of the silicon layer where the transistor is to be formed with the edges of the photoresist area being along the edges of (100) crystallographic planes which are perpendicular to the surface of the silicon layer. The portion of the silicon layer around the photoresist layer is etched with an anisotropic plasma etch which etches the silicon layer along the (100) crystallographic planes which are perpendicular to the surface of the silicon layer to form an island of the silicon.Type: GrantFiled: September 19, 1985Date of Patent: May 5, 1987Assignee: RCA CorporationInventors: Ronald K. Smeltzer, Wesley H. Morris
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Patent number: H1435Abstract: An SOI/SOS thin film MOS mesa architecture has its body/channel region extended beyond the source and drain regions and the impurity concentration is increased at a selected portion (e.g. an end portion) of the extended body region, so as to provide both a body tie access location which enables the body/channel region to be terminated to a prescribed bias voltage (e.g. Vss), and a channel stop region that is effective to functionally interrupt a current leakage path or `parasitic` N-channel that may be induced along sidewall surface of the P-type material of the body/channel region. In another embodiment, ionizing radiation-induced inversion of the sidewalls of the P-type body/channel region is prevented by an asymmetric sidewall channel stop structure formed in opposite end portions of the source region.Type: GrantFiled: October 21, 1991Date of Patent: May 2, 1995Inventors: Richard D. Cherne, Jack E. Clark, II, Glenn A. Dejong, Richard L. Lichtel, Wesley H. Morris, William H. Speece