Abstract: Silicon photonic integrated circuit (PIC) on a multi-zone semiconductor on insulator (SOI) substrate having at least a first zone and a second zone. Various optical devices of the PIC may be located above certain substrate zones that are most suitable. A first length of a photonic waveguide structure comprises the crystalline silicon and is within the first zone, while a second length of the waveguide structure is within the second zone. Within a first zone, the crystalline silicon layer is spaced apart from an underlying substrate material by a first thickness of dielectric material. Within the second zone, the crystalline silicon layer is spaced apart from the underlying substrate material by a second thickness of the dielectric material.

Abstract: Gallium nitride (GaN) layer on substrate carburization for integrated circuit technology is described. In an example, an integrated circuit structure includes a substrate including silicon. A layer comprising silicon and carbon is above the substrate. A layer comprising gallium and nitrogen is on the layer comprising silicon and carbon.

Abstract: Silicon photonic integrated circuit (PIC) on a multi-zone semiconductor on insulator (SOI) substrate having at least a first zone and a second zone. Various optical devices of the PIC may be located above certain substrate zones that are most suitable. A first length of a photonic waveguide structure comprises the crystalline silicon and is within the first zone, while a second length of the waveguide structure is within the second zone. Within a first zone, the crystalline silicon layer is spaced apart from an underlying substrate material by a first thickness of dielectric material. Within the second zone, the crystalline silicon layer is spaced apart from the underlying substrate material by a second thickness of the dielectric material.

Abstract: A method is provided for processing the back side of a semiconductor wafer after the wafer has been lapped. The process includes grinding the back side of the wafer to remove wafer material, to substantially eliminate lap damage from the back side of the wafer. The back side of the wafer may then be cleaned, etched, and polished, after which the front side of the wafer is polished. The back side grinding may be accomplished after the lapping without any other step of substantial removal of wafer material. The polishing of the back side of the wafer may be performed with a CMP machine and may produce a specular surface, visually free of damage under haze lamp inspection, with removal of about 0.5 microns of wafer material. After polishing the front side of the wafer, an epitaxial layer may be produced on the front side of the wafer.

Abstract: A method is provided for processing the back side of a semiconductor wafer after the wafer has been lapped. The process includes grinding the back side of the wafer to remove wafer material, to substantially eliminate lap damage from the back side of the wafer. The back side of the wafer may then be cleaned, etched, and polished. after which the front side of the wafer is polished. The back side grinding may be accomplished after the lapping without any other step of substantial removal of wafer material. The polishing of the back side of the wafer may be performed with a CMP machine and may produce a specular surface, visually free of damage under haze lamp inspection, with removal of about 0.5 microns of wafer material. After polishing the front side of the wafer, an epitaxial layer may be produced on the front side of the wafer.