Abstract: A receiver and method for determining a characteristic from an input signal is disclosed. A characteristic is at least one selected from a group comprising preamble detect, frequency offset and timing offset. The input signal comprises an IF frequency fIF and a preamble signal which is a sequence of M similar data symbols. The data symbols have a symbol period SP, and M is an integer greater than or equal to 2. The method comprises: —receiving N subsequent samples of the input signal, the N subsequent samples representing a part of the input signal approximating the symbol period SP, —rotating N subsequent samples to obtain N rotated symbols; —correlating the N rotated symbols with P correlation functions to generate a set of N×P correlation values, P being an integer greater than or equal to 2; and, —selecting a maximum correlation value from the set of N×P correlation values and determining the characteristic.

Abstract: A receiver and method for determining a characteristic from an input signal is disclosed. A characteristic is at least one selected from a group comprising preamble detect, frequency offset and timing offset. The input signal comprises an IF frequency fIF and a preamble signal which is a sequence of M similar data symbols. The data symbols have a symbol period SP, and M is an integer greater than or equal to 2. The method comprises: -receiving N subsequent samples of the input signal, the N subsequent samples representing a part of the input signal approximating the symbol period SP, -rotating N subsequent samples to obtain N rotated symbols; -correlating the N rotated symbols with P correlation functions to generate a set of N×P correlation values, P being an integer greater than or equal to 2; and, -selecting a maximum correlation value from the set of N×P correlation values and determining the characteristic.

Abstract: An Encryption processor is disclosed comprising an S-box unit, a byte permutation unit, a MixColumns unit and a key expansion unit. In an embodiment the byte permutation unit comprises a data input terminal for receiving input data, two or more row processors, each row processor having an input coupled to the input terminal and an output, and a clock gating circuit for generating for each of the two or more row processors a gated clock signal. Furthermore, a clock gated key expansion unit is disclosed. By clock gating, the power consumption of the processor is reduced which extends the battery life time in battery powered devices.