Abstract: A test circuit for a serial link receiver includes a first current source coupled to a first input of the serial link receiver, and a second current source coupled to a second input of the serial link receiver. The first current source is symmetrically matched to the second current source. A first switch of the first current source is turned on to permit a charge-retaining mechanism thereof to be charged. A second switch of the first current source is turned on to permit the retained charge retained to be asserted on the first input. The charge turns on a control switch of the first current source, through which the charge is asserted on the first input. A charge-draining mechanism of the first current source is turned on to thereafter permit the charge to be drained in a controlled manner after the charge has been asserted.

Abstract: A test circuit for a serial link receiver includes a first current source coupled to a first input of the serial link receiver, and a second current source coupled to a second input of the serial link receiver. The first current source is symmetrically matched to the second current source. A first switch of the first current source is turned on to permit a charge-retaining mechanism thereof to be charged. A second switch of the first current source is turned on to permit the retained charge retained to be asserted on the first input. The charge turns on a control switch of the first current source, through which the charge is asserted on the first input. A charge-draining mechanism of the first current source is turned on to thereafter permit the charge to be drained in a controlled manner after the charge has been asserted.

Abstract: A test circuit for a serial link receiver includes a first current source coupled to a first input of the serial link receiver, and a second current source coupled to a second input of the serial link receiver. The first current source is symmetrically matched to the second current source. A first switch of the first current source is turned on to permit a charge-retaining mechanism thereof to be charged. A second switch of the first current source is turned on to permit the retained charge retained to be asserted on the first input. The charge turns on a control switch of the first current source, through which the charge is asserted on the first input. A charge-draining mechanism of the first current source is turned on to thereafter permit the charge to be drained in a controlled manner after the charge has been asserted.

Abstract: A test circuit for a serial link receiver includes a first current source coupled to a first input of the serial link receiver, and a second current source coupled to a second input of the serial link receiver. The first current source is symmetrically matched to the second current source. A first switch of the first current source is turned on to permit a charge-retaining mechanism thereof to be charged. A second switch of the first current source is turned on to permit the retained charge retained to be asserted on the first input. The charge turns on a control switch of the first current source, through which the charge is asserted on the first input. A charge-draining mechanism of the first current source is turned on to thereafter permit the charge to be drained in a controlled manner after the charge has been asserted.

Abstract: A circuit device and method for designing a serial link receiver, which accommodates a wide input voltage range and provides tolerance to high termination voltages. The receiver is designed with a pair of RC networks connected inline between the input and the preamplifier and a common mode feedback loop, which monitors shifts in the common mode voltage and adjusts the inputs provided to the preamplifier. The circuit device maintains a flat bandwidth to accommodate all signaling rates.

Abstract: A system and method for a predriver and driver interface having scalable output drive capability with corresponding scalable power is disclosed.

Abstract: A method and system for is disclosed for reducing intersymbol interference in a stream of data bits to be transmitted over a transmission medium. Aspects of the present invention include a phase delayed clock generated from a reference clock that produces an edge on sub-bit boundaries; and a digital filter coupled to the phase delayed clock for performing equalization on the data bits, wherein the phase delayed clock causes the digital filter to perform partial clock switching, such that equalization is performed on the data bits on-sub-bit boundaries.

Abstract: A system and method is disclosed that efficiently provides standard termination blocks in an approved cell library that are flexible and customizable. A serial communications system includes a transmitter for sending a serial data signal at an output of the transmitter; a transmitter terminator, coupled to the output and responsive to a first configuration signal, to variably terminate a first selected property of the output; a receiver for processing the serial data signal at an input of the receiver, the input of the receiver coupled to the output of the transmitter; and a receiver terminator, coupled to the input of the receiver and responsive to a second configuration signal to variably terminate a second selected properly of the input.

Abstract: An apparatus and method is provided for detecting loss of differential signal carried by a pair of differential signal lines. According to the method, a common mode level is detected from voltages on the pair of differential signal lines. A threshold level is generated, referenced to the detected common mode level. A signal level is generated from the voltages on the pair of differential signal lines, the signal level being averaged over a first period of time. From the threshold level and the detected common mode level a reference level is generated, the reference level being averaged over a second period of time longer than then the first period of time. The signal level is compared to the reference level to determine if a signal is present on the pair of differential signal lines.

Abstract: A system and method is disclosed that efficiently provides standard termination blocks in an approved cell library that are flexible and customizable. A serial communications system includes a transmitter for sending a serial data signal at an output of the transmitter; a transmitter terminator, coupled to the output and responsive to a first configuration signal, to variably terminate a first selected property of the output; a receiver for processing the serial data signal at an input of the receiver, the input of the receiver coupled to the output of the transmitter; and a receiver terminator, coupled to the input of the receiver and responsive to a second configuration signal to variably terminate a second selected properly of the input.

Abstract: A system and method for a predriver and driver interface having scalable output drive capability with corresponding scalable power is disclosed.