Patents by Inventor Weston BERTRAND

Weston BERTRAND has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250191998
    Abstract: Embodiments of the present disclosure may generally relate to systems, apparatuses, techniques, and/or processes directed to packages that include stacked dies that use thermal conductivity features including thermally conductive through silicon vias (TSVs) filled with thermally conductive material located in passive areas of a first die to route heat from a first die away from a second die that is coupled with the first die. In embodiments, the first die may be referred to as a base die. Embodiments may include thermal blocks in the form of dummy dies that include TSVs at least partially filled with thermal energy conducting material such as copper, solder, or other alloy.
    Type: Application
    Filed: February 13, 2025
    Publication date: June 12, 2025
    Inventors: Weston BERTRAND, Kyle ARRINGTON, Shankar DEVASENATHIPATHY, Aaron MCCANN, Nicholas NEAL, Zhimin WAN
  • Patent number: 12266589
    Abstract: Embodiments of the present disclosure may generally relate to systems, apparatuses, techniques, and/or processes directed to packages that include stacked dies that use thermal conductivity features including thermally conductive through silicon vias (TSVs) filled with thermally conductive material located in passive areas of a first die to route heat from a first die away from a second die that is coupled with the first die. In embodiments, the first die may be referred to as a base die. Embodiments may include thermal blocks in the form of dummy dies that include TSVs at least partially filled with thermal energy conducting material such as copper, solder, or other alloy.
    Type: Grant
    Filed: April 15, 2024
    Date of Patent: April 1, 2025
    Assignee: Intel Corporation
    Inventors: Weston Bertrand, Kyle Arrington, Shankar Devasenathipathy, Aaron McCann, Nicholas Neal, Zhimin Wan
  • Publication number: 20240282667
    Abstract: Embodiments of the present disclosure may generally relate to systems, apparatuses, techniques, and/or processes directed to packages that include stacked dies that use thermal conductivity features including thermally conductive through silicon vias (TSVs) filled with thermally conductive material located in passive areas of a first die to route heat from a first die away from a second die that is coupled with the first die. In embodiments, the first die may be referred to as a base die. Embodiments may include thermal blocks in the form of dummy dies that include TSVs at least partially filled with thermal energy conducting material such as copper, solder, or other alloy.
    Type: Application
    Filed: April 15, 2024
    Publication date: August 22, 2024
    Inventors: Weston BERTRAND, Kyle ARRINGTON, Shankar DEVASENATHIPATHY, Aaron MCCANN, Nicholas NEAL, Zhimin WAN
  • Patent number: 12057369
    Abstract: Embodiments of the present disclosure may generally relate to systems, apparatuses, techniques, and/or processes directed to packages that include stacked dies that use thermal conductivity features including thermally conductive through silicon vias (TSVs) filled with thermally conductive material located in passive areas of a first die to route heat from a first die away from a second die that is coupled with the first die. In embodiments, the first die may be referred to as a base die. Embodiments may include thermal blocks in the form of dummy dies that include TSVs at least partially filled with thermal energy conducting material such as copper, solder, or other alloy.
    Type: Grant
    Filed: December 23, 2022
    Date of Patent: August 6, 2024
    Assignee: Intel Corporation
    Inventors: Weston Bertrand, Kyle Arrington, Shankar Devasenathipathy, Aaron McCann, Nicholas Neal, Zhimin Wan
  • Patent number: 11854935
    Abstract: Embodiments of the present disclosure may generally relate to systems, apparatuses, techniques, and/or processes directed to packages that include stacked dies that use thermal conductivity features including thermally conductive through silicon vias (TSVs) filled with thermally conductive material located in passive areas of a first die to route heat from a first die away from a second die that is coupled with the first die. In embodiments, the first die may be referred to as a base die. Embodiments may include thermal blocks in the form of dummy dies that include TSVs at least partially filled with thermal energy conducting material such as copper, solder, or other alloy.
    Type: Grant
    Filed: February 19, 2020
    Date of Patent: December 26, 2023
    Assignee: Intel Corporation
    Inventors: Weston Bertrand, Kyle Arrington, Shankar Devasenathipathy, Aaron McCann, Nicholas Neal, Zhimin Wan
  • Publication number: 20230128903
    Abstract: Embodiments of the present disclosure may generally relate to systems, apparatuses, techniques, and/or processes directed to packages that include stacked dies that use thermal conductivity features including thermally conductive through silicon vias (TSVs) filled with thermally conductive material located in passive areas of a first die to route heat from a first die away from a second die that is coupled with the first die. In embodiments, the first die may be referred to as a base die. Embodiments may include thermal blocks in the form of dummy dies that include TSVs at least partially filled with thermal energy conducting material such as copper, solder, or other alloy.
    Type: Application
    Filed: December 23, 2022
    Publication date: April 27, 2023
    Inventors: Weston BERTRAND, Kyle ARRINGTON, Shankar DEVASENATHIPATHY, Aaron MCCANN, Nicholas NEAL, Zhimin WAN
  • Publication number: 20210257277
    Abstract: Embodiments of the present disclosure may generally relate to systems, apparatuses, techniques, and/or processes directed to packages that include stacked dies that use thermal conductivity features including thermally conductive through silicon vias (TSVs) filled with thermally conductive material located in passive areas of a first die to route heat from a first die away from a second die that is coupled with the first die. In embodiments, the first die may be referred to as a base die. Embodiments may include thermal blocks in the form of dummy dies that include TSVs at least partially filled with thermal energy conducting material such as copper, solder, or other alloy.
    Type: Application
    Filed: February 19, 2020
    Publication date: August 19, 2021
    Inventors: Weston BERTRAND, Kyle ARRINGTON, Shankar DEVASENATHIPATHY, Aaron MCCANN, Nicholas NEAL, Zhimin WAN