Abstract: The disclosure is directed to a simple, inexpensive circuit to extract the complementary metal-oxide-semiconductor (CMOS) threshold voltage (Vt) from an integrated circuit. The threshold voltage may be used elsewhere in the circuit for a variety of purposes. One example use of threshold voltage is to sense the temperature of the circuit. The CMOS Vt extraction circuit of this disclosure includes a current mirror and an arrangement of well-matched transistors and resistors that takes advantage of the square law equation. The structure of the circuit may make it well suited to applications that benefit from low-power radiation hardened circuits.

Abstract: The disclosure is directed to a simple, inexpensive circuit to extract the complementary metal-oxide-semiconductor (CMOS) threshold voltage (Vt) from an integrated circuit. The threshold voltage may be used elsewhere in the circuit for a variety of purposes. One example use of threshold voltage is to sense the temperature of the circuit. The CMOS Vt extraction circuit of this disclosure includes a current mirror and an arrangement of well-matched transistors and resistors that takes advantage of the square law equation. The structure of the circuit may make it well suited to applications that benefit from low-power radiation hardened circuits.

Abstract: This disclosure is directed to devices, integrated circuits, systems, and methods for implementing an internal body tie bias circuit in a CMOS logic circuit. In one example, a CMOS logic circuit is formed in an integrated circuit. The CMOS logic circuit includes a PMOS transistor, an NMOS transistor; and a body tie bias circuit formed in the integrated circuit. The body tie bias circuit is coupled between a body tie connection terminal of the PMOS transistor and a body tie connection terminal of the NMOS transistor.

Abstract: This disclosure is directed to devices, integrated circuits, systems, and methods for implementing an internal body tie bias circuit in a CMOS logic circuit. In one example, a CMOS logic circuit is formed in an integrated circuit. The CMOS logic circuit includes a PMOS transistor, an NMOS transistor; and a body tie bias circuit formed in the integrated circuit. The body tie bias circuit is coupled between a body tie connection terminal of the PMOS transistor and a body tie connection terminal of the NMOS transistor.

Abstract: A process, voltage, and temperature (PVT) compensation circuit and a method of continuously generating a delay measure are provided. The compensation circuit includes two delay lines, each delay line providing a delay output. The two delay lines may each include a number of delay elements, which in turn may include one or more current-starved inverters. The number of delay lines may differ between the two delay lines. The delay outputs are provided to a combining circuit that determines an offset pulse based on the two delay outputs and then averages the voltage of the offset pulse to determine a delay measure. The delay measure may be one or more currents or voltages indicating an amount of PVT compensation to apply to input or output signals of an application circuit, such as a memory-bus driver, dynamic random access memory (DRAM), a synchronous DRAM, a processor or other clocked circuit.

Abstract: Method and system for aligning a clock signal to parallel data are described. According to one embodiment, a clock shifting circuit shifts an incoming clock signal relative to an incoming data signal, and a data clocking circuit uses the shifted clock signal to reclock the incoming data signal. The clock shifting circuit may comprise a phase locked loop (PLL) coupled with multiple D flip flops (DFFs) connected in series. Divisional combinatorial logic may be disposed between DFFs in the series. Data clocking circuits may comprise one DFF to reclock each incoming data bit, a pair of DFFs to reclock each incoming data bit, or other circuits such as true-complement blocks to serve as local oscillators to mixers. Multiple shifted clock signals may be produced, such as those shifted 60, 90, 120, 180, 240, and 270 degrees relative to the incoming clock signal.

Abstract: A radiation hardened differential output buffer is partitioned into multiple stages, each including at least one current source and a bridge circuit. Each stage receives substantially the same inputs at substantially the same time, and provides substantially the same output. The outputs of each stage are connected together. As a result, if one of the stages is disrupted by SEE, the disrupted stage does not contribute enough current to the output of the differential output buffer to disrupt the output signal.

Abstract: In general, this disclosure is directed to a duty cycle correction (DCC) circuit that adjusts a falling edge of a clock signal to achieve a desired duty cycle. In some examples, the DCC circuit may generate a pulse in response to a falling edge of an input clock signal, delay the pulse based on a control voltage, adjust the falling edge of the input clock signal based on the delayed pulse to produce an output clock signal, and adjust the control voltage based on the difference between a duty cycle of the output clock signal and a desired duty cycle. Since the DCC circuit adjusts the falling edge of the clock cycle to achieve a desired duty cycle, the DCC may be incorporated into existing PLL control loops that adjust the rising edge of a clock signal without interfering with the operation of such PLL control loops.

Abstract: In general, this disclosure is directed to a duty cycle correction (DCC) circuit that adjusts a falling edge of a clock signal to achieve a desired duty cycle. In some examples, the DCC circuit may generate a pulse in response to a falling edge of an input clock signal, delay the pulse based on a control voltage, adjust the falling edge of the input clock signal based on the delayed pulse to produce an output clock signal, and adjust the control voltage based on the difference between a duty cycle of the output clock signal and a desired duty cycle. Since the DCC circuit adjusts the falling edge of the clock cycle to achieve a desired duty cycle, the DCC may be incorporated into existing PLL control loops that adjust the rising edge of a clock signal without interfering with the operation of such PLL control loops.

Abstract: In general, this disclosure is directed to a duty cycle correction (DCC) circuit that adjusts a falling edge of a clock signal to achieve a desired duty cycle. In some examples, the DCC circuit may generate a pulse in response to a falling edge of an input clock signal, delay the pulse based on a control voltage, adjust the falling edge of the input clock signal based on the delayed pulse to produce an output clock signal, and adjust the control voltage based on the difference between a duty cycle of the output clock signal and a desired duty cycle. Since the DCC circuit adjusts the falling edge of the clock cycle to achieve a desired duty cycle, the DCC may be incorporated into existing PLL control loops that adjust the rising edge of a clock signal without interfering with the operation of such PLL control loops.

Abstract: A process, voltage, and temperature (PVT) compensation circuit and a method of continuously generating a delay measure are provided. The compensation circuit includes two delay lines, each delay line providing a delay output. The two delay lines may each include a number of delay elements, which in turn may include one or more current-starved inverters. The number of delay lines may differ between the two delay lines. The delay outputs are provided to a combining circuit that determines an offset pulse based on the two delay outputs and then averages the voltage of the offset pulse to determine a delay measure. The delay measure may be one or more currents or voltages indicating an amount of PVT compensation to apply to input or output signals of an application circuit, such as a memory-bus driver, dynamic random access memory (DRAM), a synchronous DRAM, a processor or other clocked circuit.

Abstract: A body-tied MOSFET device and method of fabrication are presented. In the method of fabrication, oxygen diffuses and reacts down a first axis of a pFET or nFET. This results in a partial oxidation of a buried-oxide/silicon island interface. The partial oxidation produces a thickness variation in the silicon island that creates a stress along the first axis. The stress along the first axis modifies a device characteristic of the FET. Oxidation along a second, perpendicular, axis may also be inhibited. The partial oxidation may be incorporated in SOI and STI based process flows. In addition, a dual-gate oxidation process may further enhance device characteristics.

Abstract: A method for operating a Phase Locked Loop (PLL) that mitigates radiation event influence on a phase signal. The method is implemented on a PLL having two loop filters. The first filter is a proportional (resistive) loop filter that is operated so that it scales and/or clips the influence out of the phase signal and produces a fine tuning signal. The second filter, on the other hand, is an integral (capacitive) loop filter that dampens the influence and produces a coarse tuning signal. A summing node may then combine the fine and coarse tuning signals and communicate the combined output signal to a VCO. Because the phase signal has been separately filtered, the VCO produces a waveform that is less prone to cause the PLL to report a loss of lock.

Abstract: A radiation hardened differential output buffer is partitioned into multiple stages, each including at least one current source and a bridge circuit. Each stage receives substantially the same inputs at substantially the same time, and provides substantially the same output. The outputs of each stage are connected together. As a result, if one of the stages is disrupted by SEE, the disrupted stage does not contribute enough current to the output of the differential output buffer to disrupt the output signal.

Abstract: A static random access memory (SRAM) cell with single event and soft error protection using ferroelectric material is presented. The SRAM cell comprises two inverters in a mutual feedback loop, with the output of each of the inverters coupled to the input of the other. A ferroelectric capacitor is coupled to the output of one of the inverters in order to induce an RC delay and provide single event upset (SEU), single event effect (SEE), single event transient (SET), and soft error protection. In addition, a method is presented where ferroelectric capacitor of the system is fabricated after the underlayers of the SRAM cell have been implemented in order to avoid substantial changes to standard underlayer processing.

Abstract: A method and device for a vertically integrated delay element are presented. The vertically integrated delay element includes a portion of an interconnect sandwich. The interconnect sandwich includes dielectric layers and metal layers. The portion of the interconnect sandwich is used to form a capacitor, such as a Metal Insulator Metal (MIM) capacitor, in one or more of the dielectric and metal layers of the interconnect sandwich. The capacitor increases the RC delay time of the delay element. The capacitor is also coupled to a Field Effect Transistor (FET). The FET has an increased drain resistance that may be used to further increase the RC delay of the delay element.

Abstract: A circuit generally comprising a core circuit and a test access port circuit. The core circuit may be configurable among a plurality of functions in response to a signal. The test access port circuit may be configured to determine an identification value in response to the signal.

Abstract: Embodiments of the present invention relate to a low voltage differential signal driver (LVDS) circuit which comprises a current source, logic controlled switches for controlling the driver's output, an electronic load circuit coupled across the circuit, and a common-mode resistor feedback circuit coupled across the circuit, in parallel with the RC load, for tuning the driver's impedance. The driver is enabled to operate without op-amps and achieves optimum performance at 1.8 v supply voltages.

Abstract: A scalable process transmitter architecture includes a unitized sensor module and an optional scalable transmitter. The sensor module has a sensor output that is configurable which can connect locally to a scalable transmitter module to form a transmitter, or can be wired directly to a remote receiver. The scalable transmitter can mount on the unitized sensor module and generates a scalable output for a remote receiver. The transmitter module can provide more advanced features for specific applications.

Abstract: A scalable process transmitter architecture includes a unitized sensor module and an optional scalable transmitter. The sensor module has a sensor output that is configurable which can connect locally to a scalable transmitter module to form a transmitter, or can be wired directly to a remote receiver. The scalable transmitter can mount on the unitized sensor module and generates a scalable output for a remote receiver. The transmitter module can provide more advanced features for specific applications.