Patents by Inventor Weston Roper

Weston Roper has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10139849
    Abstract: The disclosure is directed to a simple, inexpensive circuit to extract the complementary metal-oxide-semiconductor (CMOS) threshold voltage (Vt) from an integrated circuit. The threshold voltage may be used elsewhere in the circuit for a variety of purposes. One example use of threshold voltage is to sense the temperature of the circuit. The CMOS Vt extraction circuit of this disclosure includes a current mirror and an arrangement of well-matched transistors and resistors that takes advantage of the square law equation. The structure of the circuit may make it well suited to applications that benefit from low-power radiation hardened circuits.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: November 27, 2018
    Assignee: Honeywell International Inc.
    Inventors: Xiaoxin Feng, Weston Roper
  • Publication number: 20180307262
    Abstract: The disclosure is directed to a simple, inexpensive circuit to extract the complementary metal-oxide-semiconductor (CMOS) threshold voltage (Vt) from an integrated circuit. The threshold voltage may be used elsewhere in the circuit for a variety of purposes. One example use of threshold voltage is to sense the temperature of the circuit. The CMOS Vt extraction circuit of this disclosure includes a current mirror and an arrangement of well-matched transistors and resistors that takes advantage of the square law equation. The structure of the circuit may make it well suited to applications that benefit from low-power radiation hardened circuits.
    Type: Application
    Filed: April 25, 2017
    Publication date: October 25, 2018
    Inventors: Xiaoxin Feng, Weston Roper
  • Patent number: 8975952
    Abstract: This disclosure is directed to devices, integrated circuits, systems, and methods for implementing an internal body tie bias circuit in a CMOS logic circuit. In one example, a CMOS logic circuit is formed in an integrated circuit. The CMOS logic circuit includes a PMOS transistor, an NMOS transistor; and a body tie bias circuit formed in the integrated circuit. The body tie bias circuit is coupled between a body tie connection terminal of the PMOS transistor and a body tie connection terminal of the NMOS transistor.
    Type: Grant
    Filed: November 13, 2012
    Date of Patent: March 10, 2015
    Assignee: Honeywell International Inc.
    Inventors: Paul S. Fechner, Weston Roper, James D. Seefeldt
  • Publication number: 20140132306
    Abstract: This disclosure is directed to devices, integrated circuits, systems, and methods for implementing an internal body tie bias circuit in a CMOS logic circuit. In one example, a CMOS logic circuit is formed in an integrated circuit. The CMOS logic circuit includes a PMOS transistor, an NMOS transistor; and a body tie bias circuit formed in the integrated circuit. The body tie bias circuit is coupled between a body tie connection terminal of the PMOS transistor and a body tie connection terminal of the NMOS transistor.
    Type: Application
    Filed: November 13, 2012
    Publication date: May 15, 2014
    Applicant: HONEYWELL INTERNATIONAL INC.
    Inventors: Paul S. Fechner, Weston Roper, James D. Seefeldt
  • Patent number: 8390352
    Abstract: A process, voltage, and temperature (PVT) compensation circuit and a method of continuously generating a delay measure are provided. The compensation circuit includes two delay lines, each delay line providing a delay output. The two delay lines may each include a number of delay elements, which in turn may include one or more current-starved inverters. The number of delay lines may differ between the two delay lines. The delay outputs are provided to a combining circuit that determines an offset pulse based on the two delay outputs and then averages the voltage of the offset pulse to determine a delay measure. The delay measure may be one or more currents or voltages indicating an amount of PVT compensation to apply to input or output signals of an application circuit, such as a memory-bus driver, dynamic random access memory (DRAM), a synchronous DRAM, a processor or other clocked circuit.
    Type: Grant
    Filed: April 6, 2009
    Date of Patent: March 5, 2013
    Assignee: Honeywell International Inc.
    Inventors: James Seefeldt, Xiaoxin Feng, Weston Roper
  • Patent number: 8355478
    Abstract: Method and system for aligning a clock signal to parallel data are described. According to one embodiment, a clock shifting circuit shifts an incoming clock signal relative to an incoming data signal, and a data clocking circuit uses the shifted clock signal to reclock the incoming data signal. The clock shifting circuit may comprise a phase locked loop (PLL) coupled with multiple D flip flops (DFFs) connected in series. Divisional combinatorial logic may be disposed between DFFs in the series. Data clocking circuits may comprise one DFF to reclock each incoming data bit, a pair of DFFs to reclock each incoming data bit, or other circuits such as true-complement blocks to serve as local oscillators to mixers. Multiple shifted clock signals may be produced, such as those shifted 60, 90, 120, 180, 240, and 270 degrees relative to the incoming clock signal.
    Type: Grant
    Filed: May 29, 2009
    Date of Patent: January 15, 2013
    Assignee: Honeywell International Inc.
    Inventors: James Douglas Seefeldt, Weston Roper, James Hansen
  • Patent number: 8115515
    Abstract: A radiation hardened differential output buffer is partitioned into multiple stages, each including at least one current source and a bridge circuit. Each stage receives substantially the same inputs at substantially the same time, and provides substantially the same output. The outputs of each stage are connected together. As a result, if one of the stages is disrupted by SEE, the disrupted stage does not contribute enough current to the output of the differential output buffer to disrupt the output signal.
    Type: Grant
    Filed: March 28, 2006
    Date of Patent: February 14, 2012
    Assignee: Honeywell International Inc.
    Inventor: Weston Roper
  • Publication number: 20110109354
    Abstract: In general, this disclosure is directed to a duty cycle correction (DCC) circuit that adjusts a falling edge of a clock signal to achieve a desired duty cycle. In some examples, the DCC circuit may generate a pulse in response to a falling edge of an input clock signal, delay the pulse based on a control voltage, adjust the falling edge of the input clock signal based on the delayed pulse to produce an output clock signal, and adjust the control voltage based on the difference between a duty cycle of the output clock signal and a desired duty cycle. Since the DCC circuit adjusts the falling edge of the clock cycle to achieve a desired duty cycle, the DCC may be incorporated into existing PLL control loops that adjust the rising edge of a clock signal without interfering with the operation of such PLL control loops.
    Type: Application
    Filed: October 12, 2010
    Publication date: May 12, 2011
    Applicant: Honeywell International Inc.
    Inventors: Xiaoxin Feng, Weston Roper, James D. Seefeldt
  • Publication number: 20100308878
    Abstract: In general, this disclosure is directed to a duty cycle correction (DCC) circuit that adjusts a falling edge of a clock signal to achieve a desired duty cycle. In some examples, the DCC circuit may generate a pulse in response to a falling edge of an input clock signal, delay the pulse based on a control voltage, adjust the falling edge of the input clock signal based on the delayed pulse to produce an output clock signal, and adjust the control voltage based on the difference between a duty cycle of the output clock signal and a desired duty cycle. Since the DCC circuit adjusts the falling edge of the clock cycle to achieve a desired duty cycle, the DCC may be incorporated into existing PLL control loops that adjust the rising edge of a clock signal without interfering with the operation of such PLL control loops.
    Type: Application
    Filed: June 3, 2009
    Publication date: December 9, 2010
    Applicant: Honeywell International Inc.
    Inventors: Xiaoxin Feng, Weston Roper, James D. Seefeldt
  • Patent number: 7839195
    Abstract: In general, this disclosure is directed to a duty cycle correction (DCC) circuit that adjusts a falling edge of a clock signal to achieve a desired duty cycle. In some examples, the DCC circuit may generate a pulse in response to a falling edge of an input clock signal, delay the pulse based on a control voltage, adjust the falling edge of the input clock signal based on the delayed pulse to produce an output clock signal, and adjust the control voltage based on the difference between a duty cycle of the output clock signal and a desired duty cycle. Since the DCC circuit adjusts the falling edge of the clock cycle to achieve a desired duty cycle, the DCC may be incorporated into existing PLL control loops that adjust the rising edge of a clock signal without interfering with the operation of such PLL control loops.
    Type: Grant
    Filed: June 3, 2009
    Date of Patent: November 23, 2010
    Assignee: Honeywell International Inc.
    Inventors: Xiaoxin Feng, Weston Roper, James D. Seefeldt
  • Publication number: 20100253406
    Abstract: A process, voltage, and temperature (PVT) compensation circuit and a method of continuously generating a delay measure are provided. The compensation circuit includes two delay lines, each delay line providing a delay output. The two delay lines may each include a number of delay elements, which in turn may include one or more current-starved inverters. The number of delay lines may differ between the two delay lines. The delay outputs are provided to a combining circuit that determines an offset pulse based on the two delay outputs and then averages the voltage of the offset pulse to determine a delay measure. The delay measure may be one or more currents or voltages indicating an amount of PVT compensation to apply to input or output signals of an application circuit, such as a memory-bus driver, dynamic random access memory (DRAM), a synchronous DRAM, a processor or other clocked circuit.
    Type: Application
    Filed: April 6, 2009
    Publication date: October 7, 2010
    Applicant: Honeywell International Inc.
    Inventors: James Seefeldt, Xiaoxin Feng, Weston Roper
  • Publication number: 20070257310
    Abstract: A body-tied MOSFET device and method of fabrication are presented. In the method of fabrication, oxygen diffuses and reacts down a first axis of a pFET or nFET. This results in a partial oxidation of a buried-oxide/silicon island interface. The partial oxidation produces a thickness variation in the silicon island that creates a stress along the first axis. The stress along the first axis modifies a device characteristic of the FET. Oxidation along a second, perpendicular, axis may also be inhibited. The partial oxidation may be incorporated in SOI and STI based process flows. In addition, a dual-gate oxidation process may further enhance device characteristics.
    Type: Application
    Filed: May 2, 2006
    Publication date: November 8, 2007
    Applicant: Honeywell International Inc.
    Inventors: Weston Roper, Eric Vogt
  • Publication number: 20070247234
    Abstract: A method for operating a Phase Locked Loop (PLL) that mitigates radiation event influence on a phase signal. The method is implemented on a PLL having two loop filters. The first filter is a proportional (resistive) loop filter that is operated so that it scales and/or clips the influence out of the phase signal and produces a fine tuning signal. The second filter, on the other hand, is an integral (capacitive) loop filter that dampens the influence and produces a coarse tuning signal. A summing node may then combine the fine and coarse tuning signals and communicate the combined output signal to a VCO. Because the phase signal has been separately filtered, the VCO produces a waveform that is less prone to cause the PLL to report a loss of lock.
    Type: Application
    Filed: April 4, 2006
    Publication date: October 25, 2007
    Applicant: Honeywell International Inc.
    Inventor: Weston Roper
  • Publication number: 20070236246
    Abstract: A radiation hardened differential output buffer is partitioned into multiple stages, each including at least one current source and a bridge circuit. Each stage receives substantially the same inputs at substantially the same time, and provides substantially the same output. The outputs of each stage are connected together. As a result, if one of the stages is disrupted by SEE, the disrupted stage does not contribute enough current to the output of the differential output buffer to disrupt the output signal.
    Type: Application
    Filed: March 28, 2006
    Publication date: October 11, 2007
    Applicant: Honeywell International Inc.
    Inventor: Weston Roper
  • Publication number: 20070103961
    Abstract: A static random access memory (SRAM) cell with single event and soft error protection using ferroelectric material is presented. The SRAM cell comprises two inverters in a mutual feedback loop, with the output of each of the inverters coupled to the input of the other. A ferroelectric capacitor is coupled to the output of one of the inverters in order to induce an RC delay and provide single event upset (SEU), single event effect (SEE), single event transient (SET), and soft error protection. In addition, a method is presented where ferroelectric capacitor of the system is fabricated after the underlayers of the SRAM cell have been implemented in order to avoid substantial changes to standard underlayer processing.
    Type: Application
    Filed: November 7, 2005
    Publication date: May 10, 2007
    Applicant: Honeywell International Inc.
    Inventors: Weston Roper, Cheisan Yue
  • Publication number: 20070103965
    Abstract: A method and device for a vertically integrated delay element are presented. The vertically integrated delay element includes a portion of an interconnect sandwich. The interconnect sandwich includes dielectric layers and metal layers. The portion of the interconnect sandwich is used to form a capacitor, such as a Metal Insulator Metal (MIM) capacitor, in one or more of the dielectric and metal layers of the interconnect sandwich. The capacitor increases the RC delay time of the delay element. The capacitor is also coupled to a Field Effect Transistor (FET). The FET has an increased drain resistance that may be used to further increase the RC delay of the delay element.
    Type: Application
    Filed: November 7, 2005
    Publication date: May 10, 2007
    Applicant: Honeywell International Inc.
    Inventor: Weston Roper
  • Patent number: 7131033
    Abstract: A circuit generally comprising a core circuit and a test access port circuit. The core circuit may be configurable among a plurality of functions in response to a signal. The test access port circuit may be configured to determine an identification value in response to the signal.
    Type: Grant
    Filed: June 21, 2002
    Date of Patent: October 31, 2006
    Assignee: Cypress Semiconductor Corp.
    Inventors: Weston Roper, Edward L. Grivna
  • Patent number: 6898980
    Abstract: A scalable process transmitter architecture includes a unitized sensor module and an optional scalable transmitter. The sensor module has a sensor output that is configurable which can connect locally to a scalable transmitter module to form a transmitter, or can be wired directly to a remote receiver. The scalable transmitter can mount on the unitized sensor module and generates a scalable output for a remote receiver. The transmitter module can provide more advanced features for specific applications.
    Type: Grant
    Filed: May 27, 2003
    Date of Patent: May 31, 2005
    Assignee: Rosemount Inc.
    Inventors: Steven M. Behm, Dale S. Davis, Mark C. Fandrey, Roger L. Frick, Robert C. Hedtke, Richard L. Nelson, Scott D. Nelson, Weston Roper, Theodore H. Schnaare, John P. Schulte, Mark S. Schumacher
  • Patent number: 6900663
    Abstract: Embodiments of the present invention relate to a low voltage differential signal driver (LVDS) circuit which comprises a current source, logic controlled switches for controlling the driver's output, an electronic load circuit coupled across the circuit, and a common-mode resistor feedback circuit coupled across the circuit, in parallel with the RC load, for tuning the driver's impedance. The driver is enabled to operate without op-amps and achieves optimum performance at 1.8 v supply voltages.
    Type: Grant
    Filed: November 4, 2002
    Date of Patent: May 31, 2005
    Assignee: Cypress Semiconductor Corporation
    Inventors: Weston Roper, Xiaoxin Feng
  • Publication number: 20040089075
    Abstract: A scalable process transmitter architecture includes a unitized sensor module and an optional scalable transmitter. The sensor module has a sensor output that is configurable which can connect locally to a scalable transmitter module to form a transmitter, or can be wired directly to a remote receiver. The scalable transmitter can mount on the unitized sensor module and generates a scalable output for a remote receiver. The transmitter module can provide more advanced features for specific applications.
    Type: Application
    Filed: May 27, 2003
    Publication date: May 13, 2004
    Inventors: Steven M. Behm, Dale S. Davis, Mark C. Fandrey, Roger L. Frick, Robert C. Hedtke, Richard L. Nelson, Scott D. Nelson, Weston Roper, Theodore H. Schnaare, John P. Schulte, Mark S. Schumacher