Abstract: The fabrication of a printed circuit board (26) usually includes the step of testing the board with a testing machine (24) to verify operability. The testing machine accomplishes such testing by transmitting test signals to the board via a transmission line (36) and then analyzing each response signals returned from the board in response to the test signals. To reduce the incidence of error, the testing machine (24) is compensated for the propagation delay of the line (12) which is measured by launching a first string of pulses into one end of the line whose opposite end is left open. A second string of pulses is sinultaneously launched into a programmable delay line (16) which delays each second pulse by an adjustable interval. After the generation of each first and second pulse, a check is made whether the first pulse has been reflected back to the first end of the transmission line at the same time the second pulse reaches the output of the delay line.

Abstract: The fabrication of a printed circuit board (26) usually includes the step of testing the board with a testing machine (24) to verify operability. The testing machine accomplishes such testing by transmitting test signals to the board via a transmission line (36) and then analyzing each response signals returned from the board in response to the test signals. To reduce the incidence of error, the testing machine (24) is compensated for the propagation delay of the line (12) which is measured by launching a first string of pulses into one end of the line whose opposite end is left open. A second string of pulses is simultaneously launched into a programmable delay line (16) which delays each second pulse by an adjustable interval. After the generation of each first and second pulse, a check is made whether the first pulse has been reflected back to the first end of the transmission line at the same time the second pulse reaches the output of the delay line.

Abstract: A determination of whether each of a pair of interconnected nodes (22) on a circuit board (12) is connected to a corresponding one of a pair of nodes (28) on a translator board (14) via a test fixture pin (18) is had by coupling one of the translator board nodes to circuit ground. The other of the pair of nodes on the translator board is coupled to the gate of a field effect transistor (FET) (34) whose gate-to-source portion is shunted by a capacitor (38). The drain-to-source portion of the FET (34) is coupled in series with a resistor (36) between circuit ground and a voltage source supplying a potential below ground potential. When continuity exists between each of the pair of nodes (22 and 28) and each of the pair of pins (18), the FET(34) conducts, causing the voltage across the resistor (36) to change. By monitoring the voltage across the resistor (36), an indication can be had as to whether continuity exists.