Patents by Inventor Whan-kyun KIM
Whan-kyun KIM has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11665970Abstract: A method of manufacturing an MRAM device, the method including forming a first magnetic layer on a substrate; forming a first tunnel barrier layer on the first magnetic layer such that the first tunnel barrier layer includes a first metal oxide, the first metal oxide being formed by oxidizing a first metal layer at a first temperature; forming a second tunnel barrier layer on the first tunnel barrier layer such that the second tunnel barrier layer includes a second metal oxide, the second metal oxide being formed by oxidizing a second metal layer at a second temperature that is greater than the first temperature; and forming a second magnetic layer on the second tunnel barrier layer.Type: GrantFiled: June 3, 2021Date of Patent: May 30, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Whan-Kyun Kim, Deok-Hyeon Kang, Woo-Jin Kim, Woo-Chang Lim, Jun-Ho Jeong
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Patent number: 11293091Abstract: A substrate processing apparatus including a chamber accommodating a substrate; a substrate support in the chamber, the substrate support supporting the substrate; a gas injector to inject an oxidizing gas for oxidizing a metal layer to be disposed on the substrate; a cooler under the substrate to cool the substrate; a target mount disposed on the substrate, the target mount including a target for performing a sputtering process; and a blocker between the target and the gas injector, the blocker shielding the target from the oxidizing gas injected from the gas injector.Type: GrantFiled: April 30, 2020Date of Patent: April 5, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Joon-Myoung Lee, Yong-Sung Park, Whan-Kyun Kim, Se-Chung Oh, Young-Man Jang
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Publication number: 20210296577Abstract: A method of manufacturing an MRAM device, the method including forming a first magnetic layer on a substrate; forming a first tunnel barrier layer on the first magnetic layer such that the first tunnel barrier layer includes a first metal oxide, the first metal oxide being formed by oxidizing a first metal layer at a first temperature; forming a second tunnel barrier layer on the first tunnel barrier layer such that the second tunnel barrier layer includes a second metal oxide, the second metal oxide being formed by oxidizing a second metal layer at a second temperature that is greater than the first temperature; and forming a second magnetic layer on the second tunnel barrier layer.Type: ApplicationFiled: June 3, 2021Publication date: September 23, 2021Inventors: Whan-Kyun KIM, Deok-Hyeon KANG, Woo-Jin KIM, Woo-Chang LIM, Jun-Ho JEONG
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Patent number: 11031549Abstract: A method of manufacturing an MRAM device, the method including forming a first magnetic layer on a substrate; forming a first tunnel barrier layer on the first magnetic layer such that the first tunnel barrier layer includes a first metal oxide, the first metal oxide being formed by oxidizing a first metal layer at a first temperature; forming a second tunnel barrier layer on the first tunnel barrier layer such that the second tunnel barrier layer includes a second metal oxide, the second metal oxide being formed by oxidizing a second metal layer at a second temperature that is greater than the first temperature; and forming a second magnetic layer on the second tunnel barrier layer.Type: GrantFiled: September 2, 2020Date of Patent: June 8, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Whan-Kyun Kim, Deok-Hyeon Kang, Woo-Jin Kim, Woo-Chang Lim, Jun-Ho Jeong
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Publication number: 20200403153Abstract: A method of manufacturing an MRAM device, the method including forming a first magnetic layer on a substrate; forming a first tunnel barrier layer on the first magnetic layer such that the first tunnel barrier layer includes a first metal oxide, the first metal oxide being formed by oxidizing a first metal layer at a first temperature; forming a second tunnel barrier layer on the first tunnel barrier layer such that the second tunnel barrier layer includes a second metal oxide, the second metal oxide being formed by oxidizing a second metal layer at a second temperature that is greater than the first temperature; and forming a second magnetic layer on the second tunnel barrier layer.Type: ApplicationFiled: September 2, 2020Publication date: December 24, 2020Inventors: Whan-Kyun KIM, Deok-Hyeon KANG, Woo-Jin KIM, Woo-Chang LIM, Jun-Ho JEONG
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Patent number: 10847713Abstract: A method is for manufacturing a magnetic-tunnel-junction (MTJ) device. The method includes forming a free magnetic layer over a substrate, forming a metal layer over the free magnetic layer, and oxidizing the metal layer by exposing the metal layer to an oxidation gas at a temperature of 250° K or less.Type: GrantFiled: May 3, 2019Date of Patent: November 24, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Whan Kyun Kim, Eun Sun Noh, Joon Myoung Lee, Woo Chang Lim, Jun Ho Jeong
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Patent number: 10784442Abstract: A method of manufacturing an MRAM device, the method including forming a first magnetic layer on a substrate; forming a first tunnel barrier layer on the first magnetic layer such that the first tunnel barrier layer includes a first metal oxide, the first metal oxide being formed by oxidizing a first metal layer at a first temperature; forming a second tunnel barrier layer on the first tunnel barrier layer such that the second tunnel barrier layer includes a second metal oxide, the second metal oxide being formed by oxidizing a second metal layer at a second temperature that is greater than the first temperature; and forming a second magnetic layer on the second tunnel barrier layer.Type: GrantFiled: August 28, 2018Date of Patent: September 22, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Whan-Kyun Kim, Deok-Hyeon Kang, Woo-Jin Kim, Woo-Chang Lim, Jun-Ho Jeong
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Publication number: 20200255934Abstract: A substrate processing apparatus including a chamber accommodating a substrate; a substrate support in the chamber, the substrate support supporting the substrate; a gas injector to inject an oxidizing gas for oxidizing a metal layer to be disposed on the substrate; a cooler under the substrate to cool the substrate; a target mount disposed on the substrate, the target mount including a target for performing a sputtering process; and a blocker between the target and the gas injector, the blocker shielding the target from the oxidizing gas injected from the gas injector.Type: ApplicationFiled: April 30, 2020Publication date: August 13, 2020Inventors: Joon-Myoung LEE, Yong-Sung PARK, Whan-Kyun KIM, Se-Chung OH, Young-Man JANG
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Publication number: 20200176511Abstract: Semiconductor devices may include a first memory cell on a substrate and a second memory cell on the substrate and adjacent to the first memory cell. The first memory cell may include a first reference layer, a first storage layer, a first tunnel layer between the first reference layer and the first storage layer, and a first spin-orbit torque (SOT) line in contact with the first storage layer. The second memory cell may include a second reference layer, a second storage layer, a second tunnel layer between the second reference layer and the second storage layer, a second SOT line adjacent to the second storage layer, and an enhancing layer between the second storage layer and the second SOT line.Type: ApplicationFiled: May 15, 2019Publication date: June 4, 2020Inventors: Jeong Heon PARK, WHAN KYUN KIM, JUN MYEONG LEE, JUN HO JEONG, WOONG HWAN PI
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Patent number: 10640865Abstract: A substrate processing apparatus including a chamber accommodating a substrate; a substrate support in the chamber, the substrate support supporting the substrate; a gas injector to inject an oxidizing gas for oxidizing a metal layer to be disposed on the substrate; a cooler under the substrate to cool the substrate; a target mount disposed on the substrate, the target mount including a target for performing a sputtering process; and a blocker between the target and the gas injector, the blocker shielding the target from the oxidizing gas injected from the gas injector.Type: GrantFiled: June 22, 2017Date of Patent: May 5, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Joon-Myoung Lee, Yong-Sung Park, Whan-Kyun Kim, Se-Chung Oh, Young-Man Jang
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Publication number: 20190355900Abstract: A method is for manufacturing a magnetic-tunnel-junction (MTJ) device. The method includes forming a free magnetic layer over a substrate, forming a metal layer over the free magnetic layer, and oxidizing the metal layer by exposing the metal layer to an oxidation gas at a temperature of 250° K or less.Type: ApplicationFiled: May 3, 2019Publication date: November 21, 2019Inventors: WHAN KYUN KIM, EUN SUN NOH, JOON MYOUNG LEE, WOO CHANG LIM, JUN HO JEONG
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Publication number: 20190165262Abstract: A method of manufacturing an MRAM device, the method including forming a first magnetic layer on a substrate; forming a first tunnel barrier layer on the first magnetic layer such that the first tunnel barrier layer includes a first metal oxide, the first metal oxide being formed by oxidizing a first metal layer at a first temperature; forming a second tunnel barrier layer on the first tunnel barrier layer such that the second tunnel barrier layer includes a second metal oxide, the second metal oxide being formed by oxidizing a second metal layer at a second temperature that is greater than the first temperature; and forming a second magnetic layer on the second tunnel barrier layer.Type: ApplicationFiled: August 28, 2018Publication date: May 30, 2019Inventors: Whan-Kyun KIM, Deok-Hyeon KANG, Woo-Jin KIM, Woo-Chang LIM, Jun-Ho JEONG
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Patent number: 10096650Abstract: A magnetoresistive random access memory device includes a free layer, a tunnel barrier layer, an insulation barrier layer, a pinned layer, and a vertical polarizer structure. The tunnel barrier layer and the insulation barrier layer directly contacts different surfaces of the free layer. The pinned layer structure contacts the tunnel barrier layer and includes at least one pinned layer. The vertical polarizer structure contacts the insulation barrier layer and includes a plurality of magnetization multi-layered structures sequentially stacked. Each magnetization multi-layered structure includes a non-magnetic layer and a magnetic layer sequentially stacked. The pinned layer and the magnetic layer have magnetization directions anti-parallel to each other.Type: GrantFiled: November 28, 2017Date of Patent: October 9, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kwang-Seok Kim, Kee-Won Kim, Whan-Kyun Kim, Sang-Hwan Park, Young-Man Jang
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Publication number: 20180083067Abstract: A magnetoresistive random access memory device includes a free layer, a tunnel barrier layer, an insulation barrier layer, a pinned layer, and a vertical polarizer structure. The tunnel barrier layer and the insulation barrier layer directly contacts different surfaces of the free layer. The pinned layer structure contacts the tunnel barrier layer and includes at least one pinned layer. The vertical polarizer structure contacts the insulation barrier layer and includes a plurality of magnetization multi-layered structures sequentially stacked. Each magnetization multi-layered structure includes a non-magnetic layer and a magnetic layer sequentially stacked. The pinned layer and the magnetic layer have magnetization directions anti-parallel to each other.Type: ApplicationFiled: November 28, 2017Publication date: March 22, 2018Inventors: Kwang-Seok KIM, Kee-Won KIM, Whan-Kyun KIM, Sang-Hwan PARK, Young-Man JANG
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Publication number: 20180073131Abstract: A substrate processing apparatus including a chamber accommodating a substrate; a substrate support in the chamber, the substrate support supporting the substrate; a gas injector to inject an oxidizing gas for oxidizing a metal layer to be disposed on the substrate; a cooler under the substrate to cool the substrate; a target mount disposed on the substrate, the target mount including a target for performing a sputtering process; and a blocker between the target and the gas injector, the blocker shielding the target from the oxidizing gas injected from the gas injector.Type: ApplicationFiled: June 22, 2017Publication date: March 15, 2018Inventors: Joon-Myoung LEE, Yong-Sung PARK, Whan-Kyun KIM, Se-Chung OH, Young-Man JANG
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Patent number: 9837468Abstract: A magnetoresistive random access memory device includes a free layer, a tunnel barrier layer, an insulation barrier layer, a pinned layer, and a vertical polarizer structure. The tunnel barrier layer and the insulation barrier layer directly contacts different surfaces of the free layer. The pinned layer structure contacts the tunnel barrier layer and includes at least one pinned layer. The vertical polarizer structure contacts the insulation barrier layer and includes a plurality of magnetization multi-layered structures sequentially stacked. Each magnetization multi-layered structure includes a non-magnetic layer and a magnetic layer sequentially stacked. The pinned layer and the magnetic layer have magnetization directions anti-parallel to each other.Type: GrantFiled: July 6, 2016Date of Patent: December 5, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Kwang-Seok Kim, Kee-Won Kim, Whan-Kyun Kim, Sang-Hwan Park, Young-Man Jang
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Publication number: 20170110508Abstract: A magnetoresistive random access memory device includes a free layer, a tunnel barrier layer, an insulation barrier layer, a pinned layer, and a vertical polarizer structure. The tunnel barrier layer and the insulation barrier layer directly contacts different surfaces of the free layer. The pinned layer structure contacts the tunnel barrier layer and includes at least one pinned layer. The vertical polarizer structure contacts the insulation barrier layer and includes a plurality of magnetization multi-layered structures sequentially stacked. Each magnetization multi-layered structure includes a non-magnetic layer and a magnetic layer sequentially stacked. The pinned layer and the magnetic layer have magnetization directions anti-parallel to each other.Type: ApplicationFiled: July 6, 2016Publication date: April 20, 2017Inventors: Kwang-Seok KIM, Kee-Won KIM, Whan-Kyun KIM, Sang-Hwan PARK, Young-Man JANG
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Patent number: 9576916Abstract: A high frequency circuit includes a first electronic device, a second electronic device, and a graphene interconnection unit, where at least one of a trench and a via is defined under the graphene interconnection unit.Type: GrantFiled: July 6, 2012Date of Patent: February 21, 2017Assignees: SAMSUNG ELECTRONICS CO., LTD., INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITYInventors: Hyeon-jin Shin, Jae-young Choi, Seong-chan Jun, Whan-kyun Kim, Hyung-seo Yoon, Ju-yeong Oh, Ju-hwan Lim
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Patent number: 9224787Abstract: A method for fabricating a nonvolatile memory device is provided. The method includes forming a transistor including an impurity region formed in a substrate, forming a first interlayer insulation layer covering the transistor, the first interlayer insulation layer including a protrusion overlapping the impurity region, and forming an information storage unit on the protrusion, the information storage unit exposing side surfaces of the protrusion using point cusp magnetron-physical vapor deposition (PCM-PVD) and electrically connected to the impurity region.Type: GrantFiled: February 28, 2014Date of Patent: December 29, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Whan-Kyun Kim, Young-Hyun Kim, Woo-Jin Kim
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Patent number: 9224784Abstract: A nonvolatile memory device is provided. The nonvolatile memory device comprises a plurality of impurity regions formed in a substrate, a first contact electrically connected to at least one of the impurity regions, a second contact electrically connected to at least one of the impurity regions, a first information storage portion formed at a first height from the substrate and electrically connected to the first contact, and a second information storage portion formed at a second height, which is different from the first height, from the substrate and electrically connected to the second contact.Type: GrantFiled: March 4, 2014Date of Patent: December 29, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Whan-Kyun Kim, Young-Hyun Kim, Woo-Jin Kim