Patents by Inventor Whan-kyun KIM

Whan-kyun KIM has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11665970
    Abstract: A method of manufacturing an MRAM device, the method including forming a first magnetic layer on a substrate; forming a first tunnel barrier layer on the first magnetic layer such that the first tunnel barrier layer includes a first metal oxide, the first metal oxide being formed by oxidizing a first metal layer at a first temperature; forming a second tunnel barrier layer on the first tunnel barrier layer such that the second tunnel barrier layer includes a second metal oxide, the second metal oxide being formed by oxidizing a second metal layer at a second temperature that is greater than the first temperature; and forming a second magnetic layer on the second tunnel barrier layer.
    Type: Grant
    Filed: June 3, 2021
    Date of Patent: May 30, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Whan-Kyun Kim, Deok-Hyeon Kang, Woo-Jin Kim, Woo-Chang Lim, Jun-Ho Jeong
  • Patent number: 11293091
    Abstract: A substrate processing apparatus including a chamber accommodating a substrate; a substrate support in the chamber, the substrate support supporting the substrate; a gas injector to inject an oxidizing gas for oxidizing a metal layer to be disposed on the substrate; a cooler under the substrate to cool the substrate; a target mount disposed on the substrate, the target mount including a target for performing a sputtering process; and a blocker between the target and the gas injector, the blocker shielding the target from the oxidizing gas injected from the gas injector.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: April 5, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Joon-Myoung Lee, Yong-Sung Park, Whan-Kyun Kim, Se-Chung Oh, Young-Man Jang
  • Publication number: 20210296577
    Abstract: A method of manufacturing an MRAM device, the method including forming a first magnetic layer on a substrate; forming a first tunnel barrier layer on the first magnetic layer such that the first tunnel barrier layer includes a first metal oxide, the first metal oxide being formed by oxidizing a first metal layer at a first temperature; forming a second tunnel barrier layer on the first tunnel barrier layer such that the second tunnel barrier layer includes a second metal oxide, the second metal oxide being formed by oxidizing a second metal layer at a second temperature that is greater than the first temperature; and forming a second magnetic layer on the second tunnel barrier layer.
    Type: Application
    Filed: June 3, 2021
    Publication date: September 23, 2021
    Inventors: Whan-Kyun KIM, Deok-Hyeon KANG, Woo-Jin KIM, Woo-Chang LIM, Jun-Ho JEONG
  • Patent number: 11031549
    Abstract: A method of manufacturing an MRAM device, the method including forming a first magnetic layer on a substrate; forming a first tunnel barrier layer on the first magnetic layer such that the first tunnel barrier layer includes a first metal oxide, the first metal oxide being formed by oxidizing a first metal layer at a first temperature; forming a second tunnel barrier layer on the first tunnel barrier layer such that the second tunnel barrier layer includes a second metal oxide, the second metal oxide being formed by oxidizing a second metal layer at a second temperature that is greater than the first temperature; and forming a second magnetic layer on the second tunnel barrier layer.
    Type: Grant
    Filed: September 2, 2020
    Date of Patent: June 8, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Whan-Kyun Kim, Deok-Hyeon Kang, Woo-Jin Kim, Woo-Chang Lim, Jun-Ho Jeong
  • Publication number: 20200403153
    Abstract: A method of manufacturing an MRAM device, the method including forming a first magnetic layer on a substrate; forming a first tunnel barrier layer on the first magnetic layer such that the first tunnel barrier layer includes a first metal oxide, the first metal oxide being formed by oxidizing a first metal layer at a first temperature; forming a second tunnel barrier layer on the first tunnel barrier layer such that the second tunnel barrier layer includes a second metal oxide, the second metal oxide being formed by oxidizing a second metal layer at a second temperature that is greater than the first temperature; and forming a second magnetic layer on the second tunnel barrier layer.
    Type: Application
    Filed: September 2, 2020
    Publication date: December 24, 2020
    Inventors: Whan-Kyun KIM, Deok-Hyeon KANG, Woo-Jin KIM, Woo-Chang LIM, Jun-Ho JEONG
  • Patent number: 10847713
    Abstract: A method is for manufacturing a magnetic-tunnel-junction (MTJ) device. The method includes forming a free magnetic layer over a substrate, forming a metal layer over the free magnetic layer, and oxidizing the metal layer by exposing the metal layer to an oxidation gas at a temperature of 250° K or less.
    Type: Grant
    Filed: May 3, 2019
    Date of Patent: November 24, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Whan Kyun Kim, Eun Sun Noh, Joon Myoung Lee, Woo Chang Lim, Jun Ho Jeong
  • Patent number: 10784442
    Abstract: A method of manufacturing an MRAM device, the method including forming a first magnetic layer on a substrate; forming a first tunnel barrier layer on the first magnetic layer such that the first tunnel barrier layer includes a first metal oxide, the first metal oxide being formed by oxidizing a first metal layer at a first temperature; forming a second tunnel barrier layer on the first tunnel barrier layer such that the second tunnel barrier layer includes a second metal oxide, the second metal oxide being formed by oxidizing a second metal layer at a second temperature that is greater than the first temperature; and forming a second magnetic layer on the second tunnel barrier layer.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: September 22, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Whan-Kyun Kim, Deok-Hyeon Kang, Woo-Jin Kim, Woo-Chang Lim, Jun-Ho Jeong
  • Publication number: 20200255934
    Abstract: A substrate processing apparatus including a chamber accommodating a substrate; a substrate support in the chamber, the substrate support supporting the substrate; a gas injector to inject an oxidizing gas for oxidizing a metal layer to be disposed on the substrate; a cooler under the substrate to cool the substrate; a target mount disposed on the substrate, the target mount including a target for performing a sputtering process; and a blocker between the target and the gas injector, the blocker shielding the target from the oxidizing gas injected from the gas injector.
    Type: Application
    Filed: April 30, 2020
    Publication date: August 13, 2020
    Inventors: Joon-Myoung LEE, Yong-Sung PARK, Whan-Kyun KIM, Se-Chung OH, Young-Man JANG
  • Publication number: 20200176511
    Abstract: Semiconductor devices may include a first memory cell on a substrate and a second memory cell on the substrate and adjacent to the first memory cell. The first memory cell may include a first reference layer, a first storage layer, a first tunnel layer between the first reference layer and the first storage layer, and a first spin-orbit torque (SOT) line in contact with the first storage layer. The second memory cell may include a second reference layer, a second storage layer, a second tunnel layer between the second reference layer and the second storage layer, a second SOT line adjacent to the second storage layer, and an enhancing layer between the second storage layer and the second SOT line.
    Type: Application
    Filed: May 15, 2019
    Publication date: June 4, 2020
    Inventors: Jeong Heon PARK, WHAN KYUN KIM, JUN MYEONG LEE, JUN HO JEONG, WOONG HWAN PI
  • Patent number: 10640865
    Abstract: A substrate processing apparatus including a chamber accommodating a substrate; a substrate support in the chamber, the substrate support supporting the substrate; a gas injector to inject an oxidizing gas for oxidizing a metal layer to be disposed on the substrate; a cooler under the substrate to cool the substrate; a target mount disposed on the substrate, the target mount including a target for performing a sputtering process; and a blocker between the target and the gas injector, the blocker shielding the target from the oxidizing gas injected from the gas injector.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: May 5, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joon-Myoung Lee, Yong-Sung Park, Whan-Kyun Kim, Se-Chung Oh, Young-Man Jang
  • Publication number: 20190355900
    Abstract: A method is for manufacturing a magnetic-tunnel-junction (MTJ) device. The method includes forming a free magnetic layer over a substrate, forming a metal layer over the free magnetic layer, and oxidizing the metal layer by exposing the metal layer to an oxidation gas at a temperature of 250° K or less.
    Type: Application
    Filed: May 3, 2019
    Publication date: November 21, 2019
    Inventors: WHAN KYUN KIM, EUN SUN NOH, JOON MYOUNG LEE, WOO CHANG LIM, JUN HO JEONG
  • Publication number: 20190165262
    Abstract: A method of manufacturing an MRAM device, the method including forming a first magnetic layer on a substrate; forming a first tunnel barrier layer on the first magnetic layer such that the first tunnel barrier layer includes a first metal oxide, the first metal oxide being formed by oxidizing a first metal layer at a first temperature; forming a second tunnel barrier layer on the first tunnel barrier layer such that the second tunnel barrier layer includes a second metal oxide, the second metal oxide being formed by oxidizing a second metal layer at a second temperature that is greater than the first temperature; and forming a second magnetic layer on the second tunnel barrier layer.
    Type: Application
    Filed: August 28, 2018
    Publication date: May 30, 2019
    Inventors: Whan-Kyun KIM, Deok-Hyeon KANG, Woo-Jin KIM, Woo-Chang LIM, Jun-Ho JEONG
  • Patent number: 10096650
    Abstract: A magnetoresistive random access memory device includes a free layer, a tunnel barrier layer, an insulation barrier layer, a pinned layer, and a vertical polarizer structure. The tunnel barrier layer and the insulation barrier layer directly contacts different surfaces of the free layer. The pinned layer structure contacts the tunnel barrier layer and includes at least one pinned layer. The vertical polarizer structure contacts the insulation barrier layer and includes a plurality of magnetization multi-layered structures sequentially stacked. Each magnetization multi-layered structure includes a non-magnetic layer and a magnetic layer sequentially stacked. The pinned layer and the magnetic layer have magnetization directions anti-parallel to each other.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: October 9, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kwang-Seok Kim, Kee-Won Kim, Whan-Kyun Kim, Sang-Hwan Park, Young-Man Jang
  • Publication number: 20180083067
    Abstract: A magnetoresistive random access memory device includes a free layer, a tunnel barrier layer, an insulation barrier layer, a pinned layer, and a vertical polarizer structure. The tunnel barrier layer and the insulation barrier layer directly contacts different surfaces of the free layer. The pinned layer structure contacts the tunnel barrier layer and includes at least one pinned layer. The vertical polarizer structure contacts the insulation barrier layer and includes a plurality of magnetization multi-layered structures sequentially stacked. Each magnetization multi-layered structure includes a non-magnetic layer and a magnetic layer sequentially stacked. The pinned layer and the magnetic layer have magnetization directions anti-parallel to each other.
    Type: Application
    Filed: November 28, 2017
    Publication date: March 22, 2018
    Inventors: Kwang-Seok KIM, Kee-Won KIM, Whan-Kyun KIM, Sang-Hwan PARK, Young-Man JANG
  • Publication number: 20180073131
    Abstract: A substrate processing apparatus including a chamber accommodating a substrate; a substrate support in the chamber, the substrate support supporting the substrate; a gas injector to inject an oxidizing gas for oxidizing a metal layer to be disposed on the substrate; a cooler under the substrate to cool the substrate; a target mount disposed on the substrate, the target mount including a target for performing a sputtering process; and a blocker between the target and the gas injector, the blocker shielding the target from the oxidizing gas injected from the gas injector.
    Type: Application
    Filed: June 22, 2017
    Publication date: March 15, 2018
    Inventors: Joon-Myoung LEE, Yong-Sung PARK, Whan-Kyun KIM, Se-Chung OH, Young-Man JANG
  • Patent number: 9837468
    Abstract: A magnetoresistive random access memory device includes a free layer, a tunnel barrier layer, an insulation barrier layer, a pinned layer, and a vertical polarizer structure. The tunnel barrier layer and the insulation barrier layer directly contacts different surfaces of the free layer. The pinned layer structure contacts the tunnel barrier layer and includes at least one pinned layer. The vertical polarizer structure contacts the insulation barrier layer and includes a plurality of magnetization multi-layered structures sequentially stacked. Each magnetization multi-layered structure includes a non-magnetic layer and a magnetic layer sequentially stacked. The pinned layer and the magnetic layer have magnetization directions anti-parallel to each other.
    Type: Grant
    Filed: July 6, 2016
    Date of Patent: December 5, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kwang-Seok Kim, Kee-Won Kim, Whan-Kyun Kim, Sang-Hwan Park, Young-Man Jang
  • Publication number: 20170110508
    Abstract: A magnetoresistive random access memory device includes a free layer, a tunnel barrier layer, an insulation barrier layer, a pinned layer, and a vertical polarizer structure. The tunnel barrier layer and the insulation barrier layer directly contacts different surfaces of the free layer. The pinned layer structure contacts the tunnel barrier layer and includes at least one pinned layer. The vertical polarizer structure contacts the insulation barrier layer and includes a plurality of magnetization multi-layered structures sequentially stacked. Each magnetization multi-layered structure includes a non-magnetic layer and a magnetic layer sequentially stacked. The pinned layer and the magnetic layer have magnetization directions anti-parallel to each other.
    Type: Application
    Filed: July 6, 2016
    Publication date: April 20, 2017
    Inventors: Kwang-Seok KIM, Kee-Won KIM, Whan-Kyun KIM, Sang-Hwan PARK, Young-Man JANG
  • Patent number: 9576916
    Abstract: A high frequency circuit includes a first electronic device, a second electronic device, and a graphene interconnection unit, where at least one of a trench and a via is defined under the graphene interconnection unit.
    Type: Grant
    Filed: July 6, 2012
    Date of Patent: February 21, 2017
    Assignees: SAMSUNG ELECTRONICS CO., LTD., INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY
    Inventors: Hyeon-jin Shin, Jae-young Choi, Seong-chan Jun, Whan-kyun Kim, Hyung-seo Yoon, Ju-yeong Oh, Ju-hwan Lim
  • Patent number: 9224787
    Abstract: A method for fabricating a nonvolatile memory device is provided. The method includes forming a transistor including an impurity region formed in a substrate, forming a first interlayer insulation layer covering the transistor, the first interlayer insulation layer including a protrusion overlapping the impurity region, and forming an information storage unit on the protrusion, the information storage unit exposing side surfaces of the protrusion using point cusp magnetron-physical vapor deposition (PCM-PVD) and electrically connected to the impurity region.
    Type: Grant
    Filed: February 28, 2014
    Date of Patent: December 29, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Whan-Kyun Kim, Young-Hyun Kim, Woo-Jin Kim
  • Patent number: 9224784
    Abstract: A nonvolatile memory device is provided. The nonvolatile memory device comprises a plurality of impurity regions formed in a substrate, a first contact electrically connected to at least one of the impurity regions, a second contact electrically connected to at least one of the impurity regions, a first information storage portion formed at a first height from the substrate and electrically connected to the first contact, and a second information storage portion formed at a second height, which is different from the first height, from the substrate and electrically connected to the second contact.
    Type: Grant
    Filed: March 4, 2014
    Date of Patent: December 29, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Whan-Kyun Kim, Young-Hyun Kim, Woo-Jin Kim