Abstract: The present invention relates to a method for analyzing abnormal regions on an optical recording medium. The method includes the steps of: detecting the abnormal region; determining the type of the abnormal region; and measuring the length of the abnormal region. Before playback or recording of an optical recording medium inserted in an apparatus for reading from and/or writing to optical recording media the apparatus determines the positions, lengths and types of abnormal regions on the optical recording medium. The obtained information can then be used, for example, to avoid that during playback or recording a pickup for reading and/or recording unexpectedly encounters an abnormal region. This makes the operation of the apparatus more reliable.

Abstract: The present invention relates to a method for analyzing abnormal regions on an optical recording medium. The method includes the steps of: detecting the abnormal region; determining the type of the abnormal region; and measuring the length of the abnormal region. Before playback or recording of an optical recording medium inserted in an apparatus for reading from and/or writing to optical recording media the apparatus determines the positions, lengths and types of abnormal regions on the optical recording medium. The obtained information can then be used, for example, to avoid that during playback or recording a pickup for reading and/or recording unexpectedly encounters an abnormal region. This makes the operation of the apparatus more reliable.

Abstract: The present invention relates to a method and a circuit for write pulse generation for recording on optical media, and to an apparatus for writing to optical recording media using such method. It is an object of the invention to propose a reliable and accurate method for write pulse generation with low hardware complexity. According to the invention, this object is achieved by a method for write pulse generation on the basis of a bit clock, including the steps of: dividing the bit clock by a factor n, multiplying the divided bit clock by a factor n+x or n?x with a phase-locked loop to obtain signal edges which are time-shifted relative to the bit clock, selecting a desired time-shifted signal edge, and multiplying the selected time-shifted signal edge by the factor n with a further phase-locked loop to obtain a time-shifted bit clock.