Abstract: A technique for shifting an input signal from a high-speed domain to a lower-speed domain receives a high-speed input at a high clock speed rate and shifts it into a local shift register so that the input signal may be shifted into a lower speed clock domain. A high speed clock is used to clock a shift register which receives the high-speed input and a counter is used to count the number of high speed clocks. One output of the counter is latched and another output of the counter is used to control latching of outputs of the shift register. Additional latches and a leading edge detector are clocked by a lower-speed clock having a frequency which is a sub-multiple of the frequency of the higher speed clock. An output of the leading edge detector controls the additional latches while the latched output of the counter serves as an input of the leading edge detector.

Abstract: A SERDES (serializer/deserializer) time domain multiplexer/demultiplexer multiplexes N input signals into a single output signal. In multiplexing the N input signals, each input signal utilizing its respective clock is latched in a respective one of N latches whose respective outputs are respectively inputted into N circular buffers. The outputs of the N circular buffers are inputted to a multiplexer whose output is outputted to a latch. In demultiplexing an input signal into N output signals, the input signal is latched in N respective latches whose outputs are inputted to N respective circular buffers. The outputs of the N respective circular buffers are inputted to N respective output latches. The N output latches are clocked by N respective output clock inputs which are different from the N respective input clocks used to clock the N respective input latches.