Abstract: An optical switch for switching data in a network. The switch includes a housing. The switch includes a transmitter receiver means which transmits to or receives from the network the data. The transmitter receiver means is disposed in the housing. The first optical path forms a first closed optical loop along which the data flows in a first direction. The switch includes a second optical path forming a second closed optical loop along which the data flows in a second direction. The second direction is opposite the first direction. The first and second optical paths each having a portion in which the transmitter receiver means is inserted into or removed from the first and second optical paths without disruption of switching of data by the switch. A method for switching data in a network.

Abstract: An optical switch for switching data in a network. The switch includes a housing. The switch includes a transmitter receiver means which transmits to or receives from the network the data. The transmitter receiver means is disposed in the housing. The first optical path forms a first closed optical loop along which the data flows in a first direction. The switch includes a second optical path forming a second closed optical loop along which the data flows in a second direction. The second direction is opposite the first direction. The first and second optical paths each having a portion in which the transmitter receiver means is inserted into or removed from the first and second optical paths without disruption of switching of data by the switch. A method for switching data in a network.

Abstract: A switch for switching data from a source to a destination along a network, at least a portion of which is optically based. The switch a plurality of input and output ports of optical transceivers. The switch an element connected to the input and output ports in which the data is reflected as many times as necessary until a desired output port is available for the data to be sent out to the destination. A method for transferring data in a telecommunications network. The method the steps of receiving data at a chassis of an optical switch in the network. There is the step of reflecting the data in the chassis until an output port of the switch becomes available to the data. There is the step of sending the data out the output port onto the network.

Abstract: A switch for switching data from a source to a destination along a network, at least a portion of which is optically based. The switch a plurality of input and output ports of optical transceivers. The switch an element connected to the input and output ports in which the data is reflected as many times as necessary until a desired output port is available for the data to be sent out to the destination. A method for transferring data in a telecommunications network. The method the steps of receiving data at a chassis of an optical switch in the network. There is the step of reflecting the data in the chassis until an output port of the switch becomes available to the data. There is the step of sending the data out the output port onto the network.

Abstract: A data processing system (15) including a synchronous random access memory (30) and a method for accessing the synchronous random access memory are disclosed. A digital processor (20) of the data processing system is coupled to a system clock circuit (65) that produces a system clock signal for controlling operation of the digital processor. Addressable storage cells within the synchronous random access memory are accessed in response to the system clock signal and an address select signal (ADS) to write data into the storage cells or read data out from the storage cells. Initial row and column addresses are latched into a row address buffer (48) and a column address buffer (49). The data are read out from the memory in an order corresponding to a control signal (WT) in synchronization with the system clock signal. The synchronous random access memory device may be fabricated as a dynamic storage device or as a static storage device.

Abstract: A data processing system (15) including a synchronous random access memory (30) and a method for accessing the synchronous random access memory are disclosed. A digital processor (20) of the data processing system is arranged with a system clock circuit (65) that produces a system clock signal for controlling operation of the digital processor. Addressable storage cells within the synchronous random access memory are accessed in response to the system clock signal and a single select signal such as an address select signal (ADS) to write data into the storage cells or read data out from the storage cells. The synchronous random access memory device may be fabricated as a dynamic storage device or as a static storage device.

Abstract: A synchronous memory (30), comprising a row address circuit (48,50) latches a row address signal in response to a system clock signal and a binary select signal. The row address circuit produces at least one row select signal. A column address circuit (49,51-54) latches an initial column address signal in response to the system clock signal and the binary select signal. The column address circuit produces a plurality of column select signals in synchronization with the system clock signal. A memory array (75) is arranged in rows and columns of memory cells. Each memory cell stores a respective data bit. The memory array simultaneously produces an integral multiple of M data bits in response to the row select signal and the plurality of column select signals. An output circuit (OMUX) is coupled to receive the system clock signal and the integral multiple of M data bits.

Abstract: A data processing system (15) including a synchronous random access memory (30) and a method for accessing the synchronous random access memory are disclosed. A digital processor (20) of the data processing system is coupled to with a system clock circuit (65) that produces a system clock signal for controlling operation of the digital processor. Addressable storage cells within the synchronous random access memory are accessed in response to the system clock signal and an address select signal (ADS) to write data into the storage cells or read data out from the storage cells. Initial row and column addresses are latched into a row address buffer (48) and a column address buffer (49). A number of data bits corresponding to a control signal such as a wrap length (WL) signal are read out from the memory in synchronization with the system clock signal. The synchronous random access memory device may be fabricated as a dynamic storage device or as a static storage device.

Abstract: A synchronous random access memory is arranged to be responsive directly to a system clock signal for operating synchronously with the associated microprocessor. The synchronous random access memory is further arranged to either write-in or read out data in a synchronous burst operation or synchronous wrap operation in addition to synchronous random access operations. The synchronous random access memory device may be fabricated as a dynamic storage device or as a static storage device.

Abstract: A synchronous random access memory is arranged to be responsive directly to a system clock signal for operating synchronously with the associated microprocessor. The synchronous random access memory is further arranged to either write-in or read out data in a synchronous burst operation or synchronous wrap operation in addition to synchronous random access operations. The synchronous random access memory device may be fabricated as a dynamic storage device or as a static storage device.

Abstract: A synchronous random access memory is arranged to be responsive directly to a system clock signal for operating synchronously with the associated microprocessor. The synchronous random access memory is further arranged to either write-in or read out data in a synchronous burst operation or synchronous wrap operation in addition to synchronous random access operations. The synchronous random access memory device may be fabricated as a dynamic storage device or as a static storage device.

Abstract: A synchronous random access memory is arranged to be responsive directly to a system clock signal for operating synchronously with the associated microprocessor. The synchronous random access memory is further arranged to either write-in or read out data in a synchronous burst operation or synchronous wrap operation in addition to synchronous random access operations. The synchronous random access memory device may be fabricated as a dynamic storage device or as a static storage device.