Abstract: A method of forming an integrated ferroelectric/CMOS structure which effectively separates incompatible high temperature deposition and annealing processes is provided. The method of the present invention includes separately forming a CMOS structure and a ferroelectric delivery wafer. These separate structures are then brought into contact with each and the ferroelectric film of the delivery wafer is bonded to the upper conductive electrode layer of the CMOS structure by using a low temperature anneal step. A portion of the delivery wafer is then removed providing an integrated FE/CMOS structure wherein the ferroelectric capacitor is formed on top of the CMOS structure. The capacitor is in contact with the transistor of the CMOS structure through all the wiring levels of the CMOS structure.

Abstract: A method of forming an integrated ferroelectric/CMOS structure which effectively separates incompatible high temperature deposition and annealing processes is provided. The method of the present invention includes separately forming a CMOS structure and a ferroelectric delivery wafer. These separate structures are then brought into contact with each and the ferroelectric film of the delivery wafer is bonded to the upper conductive electrode layer of the CMOS structure by using a low temperature anneal step. A portion of the delivery wafer is then removed providing an integrated FE/CMOS structure wherein the ferroelectric capacitor is formed on top of the CMOS structure. The capacitor is in contact with the transistor of the CMOS structure through all the wiring levels of the CMOS structure.

Abstract: A method of forming an integrated ferroelectric/CMOS structure which effectively separates incompatible high temperature deposition and annealing processes is provided. The method of the present invention includes separately forming a CMOS structure and a ferroelectric delivery wafer. These separate structures are then brought into contact with each and the ferroelectric film of the delivery wafer is bonded to the upper conductive electrode layer of the CMOS structure by using a low temperature anneal step. A portion of the delivery wafer is then removed providing an integrated FE/CMOS structure wherein the ferroelectric capacitor is formed on top of the CMOS structure. The capacitor is in contact with the transistor of the CMOS structure through all the wiring levels of the CMOS structure.

Abstract: A method of forming an integrated ferroelectric/CMOS structure which effectively separates incompatible high temperature deposition and annealing processes is provided. The method of the present invention includes separately forming a CMOS structure and a ferroelectric delivery wafer. These separate structures are then brought into contact with each and the ferroelectric film of the delivery wafer is bonded to the upper conductive electrode layer of the CMOS structure by using a low temperature anneal step. A portion of the delivery wafer is then removed providing an integrated FE/CMOS structure wherein the ferroelectric capacitor is formed on top of the CMOS structure. The capacitor is in contact with the transistor of the CMOS structure through all the wiring levels of the CMOS structure.

Abstract: A method of forming an integrated ferroelectric/CMOS structure which effectively separates incompatible high temperature deposition and annealing processes is provided. The method of the present invention includes separately forming a CMOS structure and a ferroelectric delivery wafer. These separate structures are then brought into contact with each and the ferroelectric film of the delivery wafer is bonded to the upper conductive electrode layer of the CMOS structure by using a low temperature anneal step. A portion of the delivery wafer is then removed providing an integrated FE/CMOS structure wherein the ferroelectric capacitor is formed on top of the CMOS structure. The capacitor is in contact with the transistor of the CMOS structure through all the wiring levels of the CMOS structure.

Abstract: An integrated ferroelectric/CMOS structure which comprises at least a ferroelectric material, a pair of electrodes in contact with opposite surfaces of the ferroelectric material, where the electrodes do not decompose at deposition or annealing, and an oxygen source layer in contact with at least one of said electrodes, said oxygen source layer being a metal oxide which at least partially decomposes during deposition and/or subsequent processing is provided as well as a method of fabricating the same.

Abstract: A method of forming an integrated ferroelectric/CMOS structure which effectively separates incompatible high temperature deposition and annealing processes is provided. The method of the present invention includes separately forming a CMOS structure and a ferroelectric delivery wafer. These separate structures are then brought into contact with each and the ferroelectric film of the delivery wafer is bonded to the upper conductive electrode layer of the CMOS structure by using a low temperature anneal step. A portion of the delivery wafer is then removed providing an integrated FE/CMOS structure wherein the ferroelectric capacitor is formed on top of the CMOS structure. The capacitor is in contact with the transistor of the CMOS structure through all the wiring levels of the CMOS structure.

Abstract: A method of forming an integrated ferroelectric/CMOS structure which effectively separates incompatible high temperature deposition and annealing processes is provided. The method of the present invention includes separately forming a CMOS structure and a ferroelectric delivery wafer. These separate structures are then brought into contact with each and the ferroelectric film of the delivery wafer is bonded to the upper conductive electrode layer of the CMOS structure by using a low temperature anneal step. A portion of the delivery wafer is then removed providing an integrated FE/CMOS structure wherein the ferroelectric capacitor is formed on top of the CMOS structure. The capacitor is in contact with the transistor of the CMOS structure through all the wiring levels of the CMOS structure.

Abstract: An alignment structure (14) and method for aligning a first circuit image region (18) of a microelectronic chip (10) with a second circuit region (20) of a wafer (12). The alignment structure comprises a plurality of passive coupling elements (22) attached to the chip and arranged in a linear array and further comprises a plurality of electrodes (24) attached to the wafer and arranged in a linear array. The electrodes are arranged into a set of first driven electrodes (46), a set of second driven electrodes (48) and a set of sensing electrodes (50). The first driven, second driven and sensing electrodes are arranged alternatingly with one another and may each include one or more plates (62). The first and second driven electrodes are driven, respectively, with sine wave signals 180 degrees out of phase with one another.

Abstract: An alignment structure (14) and method for aligning a first circuit image region (18) of a microelectronic chip (10) with a second circuit region (20) of a wafer (12). The alignment structure comprises a plurality of passive coupling elements (22) attached to the chip and arranged in a linear array and further comprises a plurality of electrodes (24) attached to the wafer and arranged in a linear array. The electrodes are arranged into a set of first driven electrodes (46), a set of second driven electrodes (48) and a set of sensing electrodes (50). The first driven, second driven and sensing electrodes are arranged alternatingly with one another and may each include one or more plates (62). The first and second driven electrodes are driven, respectively, with sine wave signals 180 degrees out of phase with one another.

Abstract: Circuit for detecting error transients in logic circuits due to atomic events or other non-recurring noise sources includes a first circuit coupled to a data line for sensing a first signal on the data line at a first point in time (T1) and a second circuit coupled to the data line for sensing the first signal on the data line at a second point in time (T2) such that a time difference between T1 and T2 is small enough so that the first signal is still present on the data line in the absence of a perturbation event and such that the time difference between T1 and T2 is large enough so that any such perturbation event is resolved. A compare circuit coupled to the first and second circuits compares the sensing of the first signal by the first and second circuits, and generates an error signal in response to a non-compare.

Abstract: A highspeed bus architecture featuring low signal levels, differential sensing, and zero net current over a four wire transmission line cluster. The bus system comprises a system for transmitting n bits of data and includes an encoding system for receiving the n bits of data and outputting m signals wherein the m signals have a zero net current, m transmission lines for carrying the m signals, and a decoding system for receiving the m signals and converting the m signals back into n bits of data, using differential amplifiers.

Abstract: An integrated ferroelectric/CMOS structure which comprises at least a ferroelectric material, a pair of electrodes in contact with opposite surfaces of the ferroelectric material, where the electrodes do not decompose at deposition or annealing, and an oxygen source layer in contact with at least one of said electrodes, said oxygen source layer being a metal oxide which at least partially decomposes during deposition and/or subsequent processing is provided as well as a method of fabricating the same.

Abstract: An integrated ferroelectric/CMOS structure which comprises at least a ferroelectric material, a pair of electrodes in contact with opposite surfaces of the ferroelectric material, where the electrodes do not decompose at deposition or annealing, and an oxygen source layer in contact with at least one of said electrodes, said oxygen source layer being a metal oxide which at least partially decomposes during deposition and/or subsequent processing is provided as well as a method of fabricating the same.

Abstract: A method of forming an integrated ferroelectric/CMOS structure which effectively separates incompatible high temperature deposition and annealing processes is provided. The method of the present invention includes separately forming a CMOS structure and a ferroelectric delivery wafer. These separate structures are then brought into contact with each and the ferroelectric film of the delivery wafer is bonded to the upper conductive electrode layer of the CMOS structure by using a low temperature anneal step. A portion of the delivery wafer is then removed providing an integrated FE/CMOS structure wherein the ferroelectric capacitor is formed on top of the CMOS structure. The capacitor is in contact with the transistor of the CMOS structure through all the wiring levels of the CMOS structure.

Abstract: An integrated circuit includes a CPU, a power management unit and plural functional units each dedicated to executing different functions. The power management unit controls the threshold voltage of the different functional units to optimize power/performance operation of the circuit and intelligent power management control responds to the instruction stream and decodes each instruction in turn. This information identifies which of the functional units are required for the particular instruction and by comparing that information to power status, the intelligent power control determines whether the functional units required to execute the command are at the optimum power level. If they are, the command is allowed to proceed, otherwise the intelligent power control either stalls the instruction sequence or modifies process speed.

Abstract: A method of forming an integrated ferroelectric/CMOS structure which effectively separates incompatible high temperature deposition and annealing processes is provided. The method of the present invention includes separately forming a CMOS structure and a ferroelectric delivery wafer. These separate structures are then brought into contact with each and the ferroelectric film of the delivery wafer is bonded to the upper conductive electrode layer of the CMOS structure by using a low temperature anneal step. A portion of the delivery wafer is then removed providing an integrated FE/CMOS structure wherein the ferroelectric capacitor is formed on top of the CMOS structure. The capacitor is in contact with the transistor of the CMOS structure through all the wiring levels of the CMOS structure.

Abstract: A method of making finger capacitors in an integrated circuit comprises forming a plurality of conductive strips in a substrate having a first dielectric constant, removing a portion of the substrate material between the conductive strips to define a space and then filling the space with a material having a second dielectric constant which is greater than the first dielectric constant. By selecting the proportion of the high and low dielectric constant materials, the capacitance of the finger capacitors can be selected to have any value from a minimum, in which very little of the original, first dielectric constant material is removed and replaced by the second dielectric constant material, to a maximum, in which all of the first dielectric constant material between the conductive strips is removed and replaced with the second dielectric constant material.

Abstract: Circuits with SOI devices are coupled to a body bias voltage via a switch for selectively connecting the body bias voltage signals to the SOI device body. NMOS or PMOS SOI devices are used for the switched body SOI device and a FET is used for the switch and the gate terminal of the SOI device is connected to the FET device. The gate of the SOI device controls the FET switch connection of the body bias voltage signals to the SOI device to adjust the threshold value of the SOI device. Logic circuits incorporating the SOI devices are also disclosed, and the fabrication process for the SOI devices as well.

Abstract: Disclosed is a system for providing broader bandwidth in microprocessor bus, board and system designs. Broader bandwidth is achieved by dividing the full spectrum of frequencies available into discrete bandwidth packages, much like radio communications. The system includes a bus that is controlled by a traffic controller that polls for communication requests on the bus and then allocates bandwidth among the devices submitting such requests.