Abstract: A test vector system (157) and method for generating and verifying test vectors for testing integrated circuit speed paths involves accessing a circuit model (160), a list of circuit paths (162) and a test vector verifier (165). A single circuit path, referred to as a selected path, is selected from the paths (162). Once logical constraints are set, hazard-free logical values and logical values for both the second test clock cycle and the first test clock cycle are justified. Test vectors are generated in response to the justified values and the test vectors are used as input to the test vector verifier. The test verifier produces patterns that provide robust delay path fault tests for the given path. The test patterns are serially shifted and double-clocked in an integrated circuit or electrical circuit manufactured in accordance with circuit model (160) to determine time delay path faults.

Abstract: A test vector generator system (157) and method for generating test vectors for testing integrated circuit speed paths involves accessing both a circuit model (160) and a list of circuit paths (162). A single circuit path, referred to as a selected path, is selected from the paths (162), and a set of logic value constraints are set for logic devices in the selected circuit path. These logical constraints are set to ensure that a proper input-to-output transition, which is used to identify speed path faults, results in response to only two clock cycles. Once logical constraints are set, hazard-free logical values and logical values for both the second test clock cycle and the first test clock cycle are justified. Test vectors are generated in response to the justified values and the test vectors are serially shifted and double-clocked in an integrated circuit or electrical circuit manufactured in accordance with circuit model (160) to determine time delay path faults.

Abstract: A test vector generator system (157) and method for generating test vectors for testing integrated circuit speed paths involves accessing both a circuit model (160) and a list of circuit paths (162). A single circuit path, referred to as a selected path, is selected from the paths (162). A set of logic value constraints is set for custom logic blocks, through the use of Boolean differences, and a set of logic value constraints is set for standard logic devices in the selected circuit path. These logical constraints are set to ensure that a proper input-to-output transition, which is used to identify speed path faults, results in response to only two clock cycles. Once logical constraints are set, hazard-free logical values and logical values for both the second test clock cycle and the first test clock cycle are justified.