Abstract: High-pressure steam supply in hydrogen production process is made more efficient by water gas shift process which comprises, in alternating sequence: (a) a reaction stage wherein a feed gas comprising CO and H2O is fed into a water gas shift reactor containing a sorbent material capable of adsorbing H2O and CO2 and wherein a product gas issuing from the reactor is collected, (b) a regeneration stage wherein CO2 is removed from the reactor, (c) a loading stage, wherein H2O is fed into the reactor; wherein said feed gas mixture has a molar ratio of H2O to CO below 1.2, and the loading stage is performed at a lower pressure than the pressure of the reaction stage.

Abstract: High-pressure steam supply in hydrogen production process is made more efficient by water gas shift process which comprises, in alternating sequence: (a) a reaction stage wherein a feed gas comprising CO and H20 is fed into a water gas shift reactor containing a sorbent material capable of adsorbing H20 and C02 and wherein a product gas issuing from the reactor is collected, (b) a regeneration stage wherein C02 is removed from the reactor, (c) a loading stage, wherein H20 is fed into the reactor; wherein said feed gas mixture has a molar ratio of H20 to CO below 1.2, and the loading stage is performed at a lower pressure than the pressure of the reaction stage.

Abstract: A data processing system is provided that includes an instruction decoder 20 responsive to a compare and branch instruction CHKA.X that performs a comparison between first and second values stored in first and second registers Rn, Rm respectively. A target branch address is determined from a pre-programmed stored value and a branch to a sub-routine is performed in dependence upon a result of the comparison.

Abstract: The present invention provides a technique for swapping data values within a data word. In particular, a single endian reverse instruction is provided to cause independent swap operations to be performed on particular sections of an input data word. The data processing apparatus of the present invention comprises a data processing unit for executing instructions which is responsive to the endian reverse instruction to apply an endian reverse operation to an input data word Rm comprising a plurality of data values.

Abstract: A data processing apparatus (2) comprising: a register data store operable to store data elements; an instruction decoder (14, 16) operable to decode an instruction with generated constant, said instruction having a data value associated therewith; a data processor (18) operable to perform data processing operations within parallel processing lanes on at least one source operand in response to a data processing instruction decoded by said instruction decoder (16); and said data processor being operable in response to said decoded instruction with generated constant and associated data value to expand at least a data portion (1210) of said associated data value, said expansion being performed in response to said instruction with generated constant and depending on a selected function, to generate a constant (1240), said generated constant (1240) forming one of said at least one source operands.

Abstract: A reactor device comprises a reaction chamber for carrying out a reaction with hydrogen (H2) as reaction product. The reactor device comprises a combustion chamber, and a hydrogen-permeable membrane, which is provided between the reaction chamber and the combustion chamber. A supply channel is provided in the combustion chamber. The supply channel is designed, for example, as a tubular supply line. The supply channel is provided with lateral supply apertures for supplying a fluid containing oxygen (O2), such as air, to the combustion chamber.

Abstract: Data processing apparatus and method perform data processing operations on floating point data elements. The data processing apparatus has processing logic for performing data processing operations on the floating point data elements, and decode logic operable to decode a data processing instruction in order to determine a corresponding data processing operation to be performed by the processing logic. The data processing instruction has an m-bit immediate value encoded therein. Further, constant generation logic is provided to perform a logical operation on the m-bit immediate value in order to generate an n-bit floating point constant for use as at least one input floating point data element for the processing logic when performing the corresponding data processing operation. The values “n” and “m” are integers, and n is greater than m. This approach provides a particularly efficient technique for generating floating point constants.

Abstract: A data processing system includes an instruction fetching circuit 2, an instruction queue 4 and further processing circuits 6. A branch target cache, which maybe a branch target address cache 8, a branch target instruction cache 10 or both, is used to store branch target addresses or blocks of instructions starting at the branch target respectively. A control circuit 12 is responsive to the contents of the instruction queue 4 when a branch instruction is encountered to determine whether or not storage resources within the branch target cache 8, 10 should be allocated to that branch instruction. Storage resources within the branch target cache 8, 10 will be allocated when the number of program instructions within the instruction queue is below a threshold number and/or the estimated execution time of the program instructions is below a threshold time.

Abstract: A data processing system includes an instruction fetching circuit 2, an instruction queue 4 and further processing circuits 6. A branch target cache, which maybe a branch target address cache 8, a branch target instruction cache 10 or both, is used to store branch target addresses or blocks of instructions starting at the branch target respectively. A control circuit 12 is responsive to the contents of the instruction queue 4 when a branch instruction is encountered to determine whether or not storage resources within the branch target cache 8, 10 should be allocated to that branch instruction. Storage resources within the branch target cache 8, 10 will be allocated when the number of program instructions within the instruction queue is below a threshold number and/or the estimated execution time of the program instructions is below a threshold time.

Abstract: A data processing system is provided that includes an instruction decoder 20 responsive to a compare and branch instruction CHKA.X that performs a comparison between first and second values stored in first and second registers Rn, Rm respectively. A target branch address is determined from a pre-programmed stored value and a branch to a sub-routine is performed in dependence upon a result of the comparison.

Abstract: The present invention provides a data processing apparatus and method for performing data processing operations on floating point data elements. The data processing apparatus has processing logic for performing data processing operations on the floating point data elements, and decode logic operable to decode a data processing instruction in order to determine a corresponding data processing operation to be performed by the processing logic. The data processing instruction has an m-bit immediate value encoded therein. Further, constant generation logic is provided to perform a logical operation on the m-bit immediate value in order to generate an n-bit floating point constant for use as at least one input floating point data element for the processing logic when performing the corresponding data processing operation. The values “n” and “m” are integers, and n is greater than m. This approach provides a particularly efficient technique for generating floating point constants.

Abstract: A data processing apparatus (2) comprising: a register data store operable to store data elements; an instruction decoder (14, 16) operable to decode an instruction with generated constant, said instruction having a data value associated therewith; a data processor. (18) operable to perform data processing operations within parallel processing lanes on at least one source operand in response to a data processing instruction decoded by said instruction decoder (16); and said data processor being operable in response to said decoded instruction with generated constant and associated data value to expand at least a data portion (1210) of said associated data value, said expansion being performed in response to said instruction with generated constant and depending on a selected function, to generate a constant (1240), said generated constant (1240) forming one of said at least one source operands.

Abstract: The present invention relates to address generation and in particular to address generation in a data processing apparatus. A data processing apparatus is disclosed. The data processing apparatus comprises: a processor core operable to process a sequence of instructions, the processor core having a plurality of pipeline stages, one of the plurality of pipeline stages being an address generation stage operable to generate an address associated with an instruction for subsequent processing by the pipeline stages, the instruction being one from a first group of instructions or a second group of instructions.

Abstract: A data processing apparatus and method are provided for transferring data values between a register file and a memory. The data processing apparatus comprises a data processing unit operable to perform data processing operations on data values, and a register file having a plurality of registers operable to store the data values for access by the data processing unit. The data processing unit is responsive to a single transfer instruction to perform multiple data value transfers between a corresponding multiple of the registers of the register file and consecutive data value addresses in a memory. The single transfer instruction provides an address identifier from which the consecutive data value addresses are derivable, and further provides for each of the data value transfers a register identifier identifying the register within the plurality of registers which is the subject of that data value transfer.

Abstract: When performing data processing operations upon data words 2, 4 including a plurality of abutting data values a0, a1, a2, a3, b0, b1, b2 and b3 the results of the operation upon one data value may influence a neighboring data value in an undesired manner. An error correcting value 34 may be determined from the input data words 2, 4 and then combined with the intermediate result 32 to correct for any undesired interactions between adjacent data values.

Abstract: The present invention provides a method, data processing system and computer program for comparing first and second floating point numbers involving providing a hierarchy of tests arranged to identify from said first and second floating point numbers whether said one or more exception conditions exist. Each test is arranged to generate a hit signal if that test predicts that one or more exception conditions exist. If the executed test generates a hit signal and is not the final test in the hierarchy, the method branches to the next test in the hierarchy, executes that test and returns to the step of determining whether the executed test has generated a hit signal. If the executed test generates a hit signal and is the final test in the hierarchy, an exception signal is generated indicating the presence of one or more exception conditions.

Abstract: The present invention provides a technique for swapping data values within a data word. In particular, a single endian reverse instruction is provided to cause independent swap operations to be performed on particular sections of an input data word. The data processing apparatus of the present invention comprises a data processing unit for executing instructions which is responsive to the endian reverse instruction to apply an endian reverse operation to an input data word Rm comprising a plurality of data values.

Abstract: A clipping and quantization technique is described for producing clipped numbers in a range of 0 to N−1 (from unclipped numbers in a range of −0.5N to (1.5N−1)), where N is 2m and m is the bit length of the desired clipped and quantized number. The most significant bit of the unclipped data value indicates whether an overflow of the permitted range has occurred and that clipping is required. The next most significant bit (m−1th) indicates which saturated value should be adopted. These properties of the unclipped data value may be exploited to generate the desired clipped and quantized numbers using logical left shifting and conditionally executed saturating instructions executing upon a general purpose processor 24. The shifting operations performed to achieve saturation operation may simultaneously yield quantization.

Abstract: A system and method are provided for organizing and managing a tree structure having a plurality of nodes representing physical entities, the tree structure defining a number of node locations, each node location being reached via a predetermined path from a root node of the tree structure. The method comprises the steps of associating first and second keys with each node to be included in the tree structure, the value of at least the first key being unique for each node, and then arranging the nodes within the tree structure by sorting the nodes with respect to both the first key and the second key, the sorting with respect to the first key being such that each node may be positioned within the tree structure at any node location along the path from the root node to the node location specified by the first key. By this approach, a search can be performed for a node within the tree structure based on specified criteria for both the first and second keys.

Abstract: A data processing system and method are provided for generating a structured listing of symbols from which encoded data values for those symbols can be determined. The data processing system comprises a list generator for generating from an input stream of symbols a first list having a plurality of entries, each entry identifying a symbol in the input stream and the frequency with which that symbol appears. A sorter is then arranged to order the entries in the first list by frequency, and a selector is arranged to select the two symbols having the lowest frequency. A new symbol generator, responsive to the selector, is used to generate a new symbol to represent the two selected symbols, and to allocate the new symbol a frequency based on the two selected symbols.