Patents by Inventor Wiley P. Kirk

Wiley P. Kirk has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7504155
    Abstract: The present invention relates generally to compositions, kits and methods of providing improved semiconductor surfaces free of dangling bonds and free of strained bonds. One method provides for preventing interfacial reactions between a semiconductor surface and metal or dielectric comprising the steps of preparing a passivated semiconductor surface using a valence-mending agent and depositing a layer of metal or dielectric on the valence-mended semiconductor surface. As further described, a semiconductor surface free of interfacial reactions between the surface and a second molecular species may include a semiconductor surface with one atomic layer of valence-mending atoms, wherein valence mending occurs after introducing the semiconductor surface to a passivating agent. The present invention also includes a kit for preventing interfacial reactions from occurring on a semiconductor surface comprising a passivating agent and an instructional manual.
    Type: Grant
    Filed: April 12, 2004
    Date of Patent: March 17, 2009
    Assignee: Board of Regents, The University of Texas System
    Inventors: Meng Tao, Wiley P. Kirk
  • Publication number: 20040266211
    Abstract: The present invention relates generally to compositions and methods of improving the interface between a semiconductor material and a dielectric. One method provides for a method of improving the interface between a dielectric and a semiconductor material comprising the steps of preparing a passivated semiconductor surface using a valence-mending agent, depositing a precursor to a dielectric on the valence-mended semiconductor surface and oxidizing the precursor to a dielectric, wherein depositing and oxidizing do not damage the valence-mended semiconductor surface. The present invention also includes a semiconductor/dielectric interface with improved capacitance-voltage characteristics comprising a semiconductor substrate having at least one surface with one atomic layer of valence-mending atoms and a dielectric deposited on the semiconductor substrate.
    Type: Application
    Filed: April 12, 2004
    Publication date: December 30, 2004
    Applicant: Board of Regents, The University of Texas System
    Inventors: Meng Tao, Wiley P. Kirk, Xiaolong Yang
  • Publication number: 20040266141
    Abstract: The present invention relates generally to compositions, kits and methods of providing improved semiconductor surfaces free of dangling bonds and free of strained bonds. One method provides for preventing interfacial reactions between a semiconductor surface and metal or dielectric comprising the steps of preparing a passivated semiconductor surface using a valence-mending agent and depositing a layer of metal or dielectric on the valence-mended semiconductor surface. As further described, a semiconductor surface free of interfacial reactions between the surface and a second molecular species may include a semiconductor surface with one atomic layer of valence-mending atoms, wherein valence mending occurs after introducing the semiconductor surface to a passivating agent. The present invention also includes a kit for preventing interfacial reactions from occurring on a semiconductor surface comprising a passivating agent and an instructional manual.
    Type: Application
    Filed: April 12, 2004
    Publication date: December 30, 2004
    Applicant: Board of Regents, The University of Texas System
    Inventors: Meng Tao, Wiley P. Kirk
  • Publication number: 20040171278
    Abstract: The present invention relates generally to a method of improving the performance of solid state devices, and specifically provides methods for passivating a semiconductor surfaces with a monolayer of passivating material.
    Type: Application
    Filed: February 28, 2003
    Publication date: September 2, 2004
    Inventors: Meng Tao, Wiley P. Kirk
  • Patent number: 6784114
    Abstract: The present invention relates generally to a method of improving the performance of solid state devices, and specifically provides methods for passivating a semiconductor surfaces with a monolayer of passivating material.
    Type: Grant
    Filed: February 28, 2003
    Date of Patent: August 31, 2004
    Assignee: Board of Regents The University of Texas System
    Inventors: Meng Tao, Wiley P. Kirk
  • Patent number: 6419742
    Abstract: A method of forming lattice matched single crystal wide bandgap II-VI compound semiconductor films over a silicon substrate includes first cleaning (10) the silicon substrate. A passivation layer is formed (18), which may comprise arsenic, germanium, or CaF2, among others. The lattice matched layer is then grown (26) on the passivation layer.
    Type: Grant
    Filed: November 15, 1994
    Date of Patent: July 16, 2002
    Assignees: Texas Instruments Incorporated, Texas A&M University System
    Inventors: Wiley P. Kirk, Joe X. Zhou, Bruce E. Gnade, Chih-Chen Cho
  • Patent number: 5614785
    Abstract: An anode plate (10) for use in a field emission flat panel display device (8) includes a transparent substrate (26) having a plurality of spaced-apart, electrically conductive regions (28) are covered by a luminescent material (24) and from the anode electrode. A getter material (29) of porous silicon is deposited on the substrate (26) between the conductive regions (28) of the anode plate (10). The getter material (29) of porous silicon is preferably electrically nonconductive, opaque, and highly porous. Included are methods of fabricating the getter material (29) on the anode plate (10).
    Type: Grant
    Filed: September 28, 1995
    Date of Patent: March 25, 1997
    Assignee: Texas Instruments Incorporated
    Inventors: Robert M. Wallace, Bruce E. Gnade, Wiley P. Kirk
  • Patent number: 5093699
    Abstract: A gated resonant tunneling diode has a semiconductor mesa formed on a semiconductor substrate, a tunneling barrier layer between the mesa and the substrate, and a gate layered over the substrate about the mesa and aligned in close proximity to the tunneling barrier layer. A control voltage on the gate laterally constricts a potential well in the tunneling barrier to control the electrical size of a channel within which tunnelling occurs across the tunneling barrier layer. Preferably the gate and the tunneling layer are disposed at the base of the mesa, and the gate makes a rectifying Schottky junction in connection with the tunneling barrier layer. The device is constructed using an anisotropic etch to form the mesa with an undercut wall and a top portion overhanging the undercut wall, and a nonconformal deposition of gate material to align the gate with the top portion of the mesa.
    Type: Grant
    Filed: March 12, 1990
    Date of Patent: March 3, 1992
    Assignee: Texas A & M University System
    Inventors: Mark H. Weichold, William B. Kinard, Wiley P. Kirk