Abstract: An integrated semiconductor circuit includes pad cells each having a connecting pad and an output driver. A transmission response of the pad cells is to be tested in a test mode. A signal transmitter is provided in order to produce periodic signal sequences. A periodic output signal from the signal transmitter is supplied as an input signal to an input of a pad cell to be tested. Through the use of an appropriate periodic signal at an output of the pad cell, the transmission response of the pad cell is tested in a frequency domain using a measurement method which employs a spectrum analyzer. This avoids complex measurements in the time domain, which have been carried out heretofore.

Abstract: A semiconductor memory of an integrated circuit has memory cells that are combined to form individually addressable normal units and redundant units for replacing normal units. The semiconductor memory has a selection circuit for selecting one of the redundant units. A non-volatile first memory unit for storing an address, which can be programmed by an energy beam, of a normal unit to be replaced is provided. A non-volatile second memory unit for storing an address, which can be programmed via electrical contact is also provided. The first and second memory units are connected to the selection circuit for transmitting their respective stored information to the selection circuit. A repair can thus be carried out on the unhoused semiconductor memory and on the housed semiconductor memory. Since only a sufficient portion of all the redundant circuits to be provided are configured in such a way, this allows a space requirement that is smaller overall.

Abstract: In a method for checking the functioning of memory cells of an integrated semiconductor memory, a first group of the memory cells is tested. The test results, separately for each tested memory cell, are buffer-stored in at least triple copies in a second group of the memory cells. A comparison is made between the copies of each of the test results and the evaluation thereof. The addresses of the respective memory cells of the second group are determined by an address transformation. The latter is configured in such a way that significant clusters of functional errors in an error-affected second group of the memory cells do not influence the result of the test method.

Abstract: In order to test a semiconductor memory, a bit fail map is generated in that a predetermined data value is written to memory cells and subsequently read out and compared with the data value that has been written. The bit fail map is buffer-stored on the semiconductor memory in a memory bank other than the one that is currently being tested. Reliability of the test method is improved since defects in different memory banks can be regarded as independent of one another. It is advantageous for the bit fail map to be stored three times in different memory banks and for a majority decision to be taken during read-out.

Abstract: A method and apparatus for processing defect addresses includes a reduced number of defect addresses to the extent necessary for later evaluation of the defect situation. Preferably, defect addresses are not stored when more than a predetermined number of defects are known for a column in the case of column-by-column checking of a matrix-type memory or per row in the case of row-by-row checking of a matrix-type memory.

Abstract: A method and apparatus for processing defect addresses includes a reduced number of defect addresses to the extent necessary for later evaluation of the defect situation. Preferably, defect addresses are not stored when more than a predetermined number of defects are known for a column in the case of column-by-column checking of a matrix-type memory or per row in the case of row-by-row checking of a matrix-type memory.

Abstract: An integrated memory has addressable memory cells combined into groups of column lines and row lines. The addresses of the memory cells each include a first address part addressing the respective groups of column lines and row lines. In a method for checking operation, the memory cells are successively tested in the intersection of two groups to ensure that there are no faults. Memory cells in another group are then tested. If a match between compared first address parts of faulty memory cells exists, the address of at least one of the faulty memory cells is processed further for evaluation purposes, and the addresses of other faulty memory cells are not processed further. This permits extensive compaction of addresses of faulty memory cells.

Abstract: In a method for checking the functioning of memory cells of an integrated semiconductor memory, a first group of the memory cells is tested. The test results, separately for each tested memory cell, are buffer-stored in at least triple copies in a second group of the memory cells. A comparison is made between the copies of each of the test results and the evaluation thereof. The addresses of the respective memory cells of the second group are determined by an address transformation. The latter is configured in such a way that significant clusters of functional errors in an error-affected second group of the memory cells do not influence the result of the test method.

Abstract: An integrated memory has addressable memory cells combined into groups of column lines and row lines. The addresses of the memory cells each include a first address part addressing the respective groups of column lines and row lines. In a method for checking operation, the memory cells are successively tested in the intersection of two groups to ensure that there are no faults. Memory cells in another group are then tested. If a match between compared first address parts of faulty memory cells exists, the address of at least one of the faulty memory cells is processed further for evaluation purposes, and the addresses of other faulty memory cells are not processed further. This permits extensive compaction of addresses of faulty memory cells.

Abstract: An integrated semiconductor memory which can be subjected to a memory cell test for determining operative and defective memory cells has addressable normal memory cells (MC) and redundant memory cells (RMC) for replacing, in each case, one of the normal memory cells (MC). A memory unit (2) for storing addresses (ADR) of defective normal memory cells (MC) serves as a buffer memory. A preprocessing device (3) has a memory device (4, 5) for storing a fixed number of addresses (ADR) of defective normal memory cells (MC). It serves for the comparison between the stored addresses (ADR) and for the outputting of an output signal (S31) according to the result of the comparison. This serves for controlling the storing operation of the memory unit (2). A suitable comparison between the addresses (ADR) allows defect information to be filtered out for a subsequent redundancy analysis, whereby the size of the memory unit (2) can be kept comparatively small.

Abstract: An integrated semiconductor memory which can be subjected to a memory cell test for determining operative and defective memory cells has addressable normal memory cells (MC) and redundant memory cells (RMC) for replacing, in each case, one of the normal memory cells (MC). A memory unit (2) for storing addresses (ADR) of defective normal memory cells (MC) serves as a buffer memory. A preprocessing device (3) has a memory device (4, 5) for storing a fixed number of addresses (ADR) of defective normal memory cells (MC). It serves for the comparison between the stored addresses (ADR) and for the outputting of an output signal (S31) according to the result of the comparison. This serves for controlling the storing operation of the memory unit (2). A suitable comparison between the addresses (ADR) allows defect information to be filtered out for a subsequent redundancy analysis, whereby the size of the memory unit (2) can be kept comparatively small.