Abstract: Photovoltaic devices such as solar cells having one or more field-effect hole or electron inversion/accumulation layers as contact regions are configured such that the electric field required for charge inversion and/or accumulation is provided by the output voltage of the photovoltaic device or that of an integrated solar cell unit. In some embodiments, a power source may be connected between a gate electrode and a contact region on the opposite side of photovoltaic device. In other embodiments, the photovoltaic device or integrated unit is self-powering.

Abstract: A method of forming a semiconductor structure is provided. The method including forming a first vertical channel on a first layer of source/drain material that is perpendicular relative to the first vertical channel, and forming a first source/drain semiconductor structure by removing one or more portions of the first layer of source/drain material such that i) the first source/drain semiconductor structure has a vertical side that is substantially planar with a vertical side of the first vertical channel and ii) a width of the source/drain is greater than a width of the first vertical channel, wherein the first source/drain semiconductor structure extends perpendicularly from its vertical side farther than the first vertical channel extends perpendicularly from its vertical side.

Abstract: Photovoltaic devices such as solar cells having one or more field-effect hole or electron inversion/accumulation layers as contact regions are configured such that the electric field required for charge inversion and/or accumulation is provided by the output voltage of the photovoltaic device or that of an integrated solar cell unit. In some embodiments, a power source may be connected between a gate electrode and a contact region on the opposite side of photovoltaic device. In other embodiments, the photovoltaic device or integrated unit is self-powering.

Abstract: Photovoltaic devices such as solar cells having one or more field-effect hole or electron inversion/accumulation layers as contact regions are configured such that the electric field required for charge inversion and/or accumulation is provided by the output voltage of the photovoltaic device or that of an integrated solar cell unit. In some embodiments, a power source may be connected between a gate electrode and a contact region on the opposite side of photovoltaic device. In other embodiments, the photovoltaic device or integrated unit is self-powering.

Abstract: An interconnect structure including a semiconductor structure on a semiconductor substrate, the semiconductor structure having a gate structure, shallow trench isolation and a source and a drain; a trench adjacent to the gate structure; a metal line adjacent to the gate structure and filling the trench, the metal line contacts one of the source and the drain; a gap in the metal line so as to create segments of the metal line; and a dielectric material filling the gap such that ends of the metal line abut the dielectric material wherein the ends of the metal line have a flat surface.

Abstract: A semiconductor structure that has adjacent transistors that share a common source/drain semiconductor structure. At least one of the adjacent transistors comprising: a vertical channel and a source/drain semiconductor structure connected to the vertical channel such that the source/drain semiconductor structure has a vertical side that is substantially planar with a vertical side of the first vertical channel. The source/drain semiconductor structure extends horizontally from its vertical side farther than the first vertical channel extends from its vertical side such that a width of the source/drain is greater than a width of the first vertical channel. The first source/drain semiconductor structure is located on a layer of substrate and the vertical channel is perpendicular relative to the layer of substrate.

Abstract: A semiconductor structure having an electrical contact that is connected to source/drain structures of two different transistors. The semiconductor structure has a vertical channel and a source/drain semiconductor structure connected to the vertical channel such that the source/drain semiconductor structure has a vertical side that is substantially planar with a vertical side of the first vertical channel. The source/drain semiconductor structure extends horizontally from its vertical side farther than the first vertical channel extends from its vertical side such that a width of the source/drain is greater than a width of the first vertical channel. The first source/drain semiconductor structure is located on a layer of substrate and the vertical channel is perpendicular relative to the layer of substrate.

Abstract: An interconnect structure including a semiconductor structure on a semiconductor substrate, the semiconductor structure having a gate structure, shallow trench isolation and a source and a drain; a trench adjacent to the gate structure; a metal line adjacent to the gate structure and filling the trench, the metal line contacts one of the source and the drain; a gap in the metal line so as to create segments of the metal line; and a dielectric material filling the gap such that ends of the metal line abut the dielectric material wherein the ends of the metal line have a flat surface.

Abstract: A gate structure in a semiconductor device includes: a gate stack formed on a substrate with three sections, a bottom portion, a top portion, and a sacrificial cap layer over the top portion; gate spacers, source and drain regions, a nitride encapsulation over top and sidewalls of the gate stack after removal of the sacrificial cap layer, an organic planarizing layer over the nitride encapsulation, planarizing the encapsulation, and silicidation performed over the source and drain regions and the bottom portion after removal of the nitride encapsulation, the organic planarizing layer, and the top portion of the gate stack.

Abstract: Photovoltaic structures are provided with field-effect inversion/accumulation layers as emitter layers induced by work-function differences between gate conductor layers and substrates thereof. Localized contact regions are in electrical communication with the gate conductors of such structures for repelling minority carriers. Such localized contact regions may include doped crystalline or polycrystalline silicon regions between the gate conductor and silicon absorption layers. Fabrication of the structures can be conducted without alignment between metal contacts and the localized contact regions or high temperature processing.

Abstract: A semiconductor device including at least one semiconductor device on a first surface of a dielectric layer, and at least one stressor structure having an intrinsic stress on a second surface of the dielectric layer. The at least one semiconductor device and the at least one stressor structure are present on opposing sides of the dielectric layer. The at least one stressor structure induces a stress on the at least one semiconductor device opposite the intrinsic stress.

Abstract: A method for forming an interconnect structure including: forming a semiconductor structure on a semiconductor substrate, the semiconductor structure having a gate structure, shallow trench isolation and a source/drain; forming a dielectric over the semiconductor structure; removing the dielectric adjacent to the gate structure to create a trench adjacent to the gate structure; depositing a metal into and filling the trench adjacent to the gate structure to form a metal line; etching the metal line to form a gap in the metal line so as to create segments of the metal line; and filling the gap with a dielectric material to enable tip-to-tip spacing between the segments of the metal line.

Abstract: A method for forming a nanowire device comprises forming a fin on a substrate, depositing a first layer of insulator material on the substrate, etching to remove portions of the first layer of insulator material to reduce a thickness of the first layer of insulator material, epitaxially growing a first layer of semiconductor material on exposed sidewall portions of the fin, depositing a second layer of insulator material on the first layer of insulator material, etching to remove portions of the second layer of insulator material to reduce a thickness of the second layer of insulator material, and etching to remove portions of the first layer of semiconductor material to expose portions of the fin and form a first nanowire and a second nanowire.

Abstract: A method for forming a nanowire device comprises forming a fin on a substrate, depositing a first layer of insulator material on the substrate, etching to remove portions of the first layer of insulator material to reduce a thickness of the first layer of insulator material, epitaxially growing a first layer of semiconductor material on exposed sidewall portions of the fin, depositing a second layer of insulator material on the first layer of insulator material, etching to remove portions of the second layer of insulator material to reduce a thickness of the second layer of insulator material, and etching to remove portions of the first layer of semiconductor material to expose portions of the fin and form a first nanowire and a second nanowire.

Abstract: A back end of line device and method for fabricating a transistor device include a substrate having an insulating layer formed thereon and a channel layer formed on the insulating layer. A gate structure is formed on the channel layer. Dopants are implanted into an upper portion of the channel layer on opposite sides of the gate structure to form shallow source and drain regions using a low temperature implantation process. An epitaxial layer is selectively grown on the shallow source and drain regions to form raised regions above the channel layer and against the gate structure using a low temperature plasma enhanced chemical vapor deposition process, wherein low temperature is less than about 400 degrees Celsius.

Abstract: A memory cell, an array of memory cells, and a method for fabricating a memory cell with multigate transistors such as fully depleted finFET or nano-wire transistors in embedded DRAM. The memory cell includes a trench capacitor, a non-planar transistor, and a self-aligned silicide interconnect electrically coupling the trench capacitor to the non-planar transistor.

Abstract: A method of forming a semiconductor structure is provided. The method including forming a first vertical channel on a first layer of source/drain material that is perpendicular relative to the first vertical channel, and forming a first source/drain semiconductor structure by removing one or more portions of the first layer of source/drain material such that i) the first source/drain semiconductor structure has a vertical side that is substantially planar with a vertical side of the first vertical channel and ii) a width of the source/drain is greater than a width of the first vertical channel, wherein the first source/drain semiconductor structure extends perpendicularly from its vertical side farther than the first vertical channel extends perpendicularly from its vertical side.

Abstract: A back end of line device and method for fabricating a transistor device include a substrate having an insulating layer formed thereon and a channel layer formed on the insulating layer. A gate structure is formed on the channel layer. Dopants are implanted into an upper portion of the channel layer on opposite sides of the gate structure to form shallow source and drain regions using a low temperature implantation process. An epitaxial layer is selectively grown on the shallow source and drain regions to form raised regions above the channel layer and against the gate structure using a low temperature plasma enhanced chemical vapor deposition process, wherein low temperature is less than about 400 degrees Celsius.

Abstract: A semiconductor structure that has adjacent transistors that share a common source/drain semiconductor structure. At least one of the adjacent transistors comprising: a vertical channel and a source/drain semiconductor structure connected to the vertical channel such that the source/drain semiconductor structure has a vertical side that is substantially planar with a vertical side of the first vertical channel. The source/drain semiconductor structure extends horizontally from its vertical side farther than the first vertical channel extends from its vertical side such that a width of the source/drain is greater than a width of the first vertical channel. The first source/drain semiconductor structure is located on a layer of substrate and the vertical channel is perpendicular relative to the layer of substrate.

Abstract: A semiconductor structure having an electrical contact that is connected to source/drain structures of two different transistors. The semiconductor structure has a vertical channel and a source/drain semiconductor structure connected to the vertical channel such that the source/drain semiconductor structure has a vertical side that is substantially planar with a vertical side of the first vertical channel. The source/drain semiconductor structure extends horizontally from its vertical side farther than the first vertical channel extends from its vertical side such that a width of the source/drain is greater than a width of the first vertical channel. The first source/drain semiconductor structure is located on a layer of substrate and the vertical channel is perpendicular relative to the layer of substrate.