Patents by Inventor Wilfried Ernst-August Haensch
Wilfried Ernst-August Haensch has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10243562Abstract: A voltage shifting circuit includes a first transistor in electrical parallel with a second transistor between an input node and an output node; a gate threshold capacitor disposed between the output node and a gate of the second transistor; and at least one of a) a downshift capacitor disposed between the input node and a drain/source of the first transistor, arranged to downshift a voltage from the input node and apply the downshifted voltage to the drain/source of the first transistor; and b) an upshift capacitor disposed between the input node and a drain/source of the second transistor, arranged to upshift a voltage from the input node and apply the upshifted voltage to the drain/source of the second transistor. This circuit is advantageously directly coupled to an input or output node of a non-complementary logic gate, of which multiple instances can be deployed in display circuitry or solar panels.Type: GrantFiled: February 28, 2017Date of Patent: March 26, 2019Assignee: International Business Machines CorporationInventors: Wilfried Ernst-August Haensch, Bahman Hekmatshoartabari
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Publication number: 20180248550Abstract: A voltage shifting circuit includes a first transistor in electrical parallel with a second transistor between an input node and an output node; a gate threshold capacitor disposed between the output node and a gate of the second transistor; and at least one of a) a downshift capacitor disposed between the input node and a drain/source of the first transistor, arranged to downshift a voltage from the input node and apply the downshifted voltage to the drain/source of the first transistor; and b) an upshift capacitor disposed between the input node and a drain/source of the second transistor, arranged to upshift a voltage from the input node and apply the upshifted voltage to the drain/source of the second transistor. This circuit is advantageously directly coupled to an input or output node of a non-complementary logic gate, of which multiple instances can be deployed in display circuitry or solar panels.Type: ApplicationFiled: February 28, 2017Publication date: August 30, 2018Inventors: Wilfried Ernst-August Haensch, Bahman Hekmatshoartabari
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Patent number: 9548385Abstract: Semiconductor devices having vertical field effect transistors with self-aligned source and drain contacts are provided, as well as methods for fabricating vertical field effect transistors with self-aligned source and drain contacts.Type: GrantFiled: February 11, 2016Date of Patent: January 17, 2017Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Wilfried Ernst-August Haensch, Ali Khakifirooz, Davood Shahrjerdi
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Patent number: 9385050Abstract: A structure comprises first and at least second fin structures are formed. Each of the first and at least second fin structures has a vertically oriented semiconductor body. The vertically oriented semiconductor body is comprised of vertical surfaces. A doped region in each of the first and at least second fin structures is comprised of a concentration of dopant ions present in the semiconductor body to form a first resistor and at least a second resistor, and a pair of merged fins formed on outer portions of the doped regions of the first and at least second fin structures. The pair of merged fins is electrically connected so that the first and at least second resistors are electrically connected in parallel with each other.Type: GrantFiled: January 6, 2011Date of Patent: July 5, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Wilfried Ernst-August Haensch, Pranita Kulkarni, Tenko Yamashita
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Patent number: 9312383Abstract: Semiconductor devices having vertical field effect transistors with self-aligned source and drain contacts are provided, as well as methods for fabricating vertical field effect transistors with self-aligned source and drain contacts.Type: GrantFiled: August 12, 2015Date of Patent: April 12, 2016Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Wilfried Ernst-August Haensch, Ali Khakifirooz, Davood Shahrjerdi
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Patent number: 9246113Abstract: A dense binary memory switch device combines the function of a pass transistor and a memory cell and has low programming and operation voltages. The device includes a charge storage region coupled to a gate electrode through a gate dielectric layer and directly contacting a channel region. The charge storage region contains quantum structures, deep traps or combinations thereof and is charged by carriers injected from injection regions that are in direct contact with the charge storage region. Fabrication of the device at low temperatures compatible with back-end-of-line processing is further disclosed.Type: GrantFiled: February 14, 2014Date of Patent: January 26, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kevin K. Chan, Tze-Chiang Chen, Kailash Gopalakrishnan, Wilfried Ernst-August Haensch, Bahman Hekmatshoartabari
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Patent number: 9245896Abstract: A dense binary memory switch device combines the function of a pass transistor and a memory cell and has low programming and operation voltages. The device includes a charge storage region coupled to a gate electrode through a gate dielectric layer and to a channel region through another dielectric layer. The charge storage region is charged by carriers injected from injection regions that are in direct contact with the charge storage region. Fabrication of the device at low temperatures compatible with back-end-of-line processing is further disclosed.Type: GrantFiled: February 14, 2014Date of Patent: January 26, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ali Afzali-Ardakani, Tze-Chiang Chen, Kailash Gopalakrishnan, Wilfried Ernst-August Haensch, Bahman Hekmatshoartabari
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Publication number: 20150236029Abstract: A dense binary memory switch device combines the function of a pass transistor and a memory cell and has low programming and operation voltages. The device includes a charge storage region coupled to a gate electrode through a gate dielectric layer and to a channel region through another dielectric layer. The charge storage region is charged by carriers injected from injection regions that are in direct contact with the charge storage region. Fabrication of the device at low temperatures compatible with back-end-of-line processing is further disclosed.Type: ApplicationFiled: February 14, 2014Publication date: August 20, 2015Applicant: International Business Machines CorporationInventors: Ali Afzali-Ardakani, Tze-Chiang Chen, Kailash Gopalakrishnan, Wilfried Ernst-August Haensch, Bahman Hekmatshoartabari
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Publication number: 20150236284Abstract: A dense binary memory switch device combines the function of a pass transistor and a memory cell and has low programming and operation voltages. The device includes a charge storage region coupled to a gate electrode through a gate dielectric layer and directly contacting a channel region. The charge storage region contains quantum structures, deep traps or combinations thereof and is charged by carriers injected from injection regions that are in direct contact with the charge storage region. Fabrication of the device at low temperatures compatible with back-end-of-line processing is further disclosed.Type: ApplicationFiled: February 14, 2014Publication date: August 20, 2015Applicant: International Business Machines CorporationInventors: Kevin K. Chan, Tze-Chiang Chen, Kailash Gopalakrishnan, Wilfried Ernst-August Haensch, Bahman Hekmatshoartabari
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Patent number: 9064748Abstract: Transistor devices having a self-aligned gate structure on transparent substrates and techniques for fabrication thereof are provided. In one aspect, a method of fabricating a transistor device includes the following steps. A channel material is formed on a transparent substrate. Source and drain electrodes are formed in contact with the channel material. A dielectric layer is deposited on the channel material. A photoresist is deposited on the dielectric layer and developed using UV light exposure through the transparent substrate. A gate metal(s) is deposited on the exposed portions of the dielectric layer and the undeveloped portions of the photoresist. The undeveloped portions of the photoresist are removed along with portions of the gate metal over the source and drain regions to form a gate of the device on the dielectric layer over the channel material which is self-aligned to the source and drain electrodes.Type: GrantFiled: July 3, 2014Date of Patent: June 23, 2015Assignee: International Business Machines CorporationInventors: Wilfried Ernst-August Haensch, Zihong Liu
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Patent number: 8969965Abstract: FinFET devices and methods for the fabrication thereof are provided. In one aspect, a method for fabricating a FET device includes the following steps. A wafer is provided having an active layer on an insulator. A plurality of fin hardmasks are patterned on the active layer. A dummy gate is placed over a central portion of the fin hardmasks. One or more doping agents are implanted into source and drain regions of the device. A dielectric filler layer is deposited around the dummy gate. The dummy gate is removed to form a trench in the dielectric filler layer. The fin hardmasks are used to etch a plurality of fins in the active layer within the trench. The doping agents are activated. A replacement gate is formed in the trench, wherein the step of activating the doping agents is performed before the step of forming the replacement gate.Type: GrantFiled: January 7, 2014Date of Patent: March 3, 2015Assignee: International Business Machines CorporationInventors: Josephine B. Chang, Michael A. Guillorn, Wilfried Ernst-August Haensch
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Publication number: 20140312298Abstract: Transistor devices having a self-aligned gate structure on transparent substrates and techniques for fabrication thereof are provided. In one aspect, a method of fabricating a transistor device includes the following steps. A channel material is formed on a transparent substrate. Source and drain electrodes are formed in contact with the channel material. A dielectric layer is deposited on the channel material. A photoresist is deposited on the dielectric layer and developed using UV light exposure through the transparent substrate. A gate metal(s) is deposited on the exposed portions of the dielectric layer and the undeveloped portions of the photoresist. The undeveloped portions of the photoresist are removed along with portions of the gate metal over the source and drain regions to form a gate of the device on the dielectric layer over the channel material which is self-aligned to the source and drain electrodes.Type: ApplicationFiled: July 3, 2014Publication date: October 23, 2014Inventors: Wilfried Ernst-August Haensch, Zihong Liu
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Patent number: 8802514Abstract: Transistor devices having a self-aligned gate structure on transparent substrates and techniques for fabrication thereof are provided. In one aspect, a method of fabricating a transistor device includes the following steps. A channel material is formed on a transparent substrate. Source and drain electrodes are formed in contact with the channel material. A dielectric layer is deposited on the channel material. A photoresist is deposited on the dielectric layer and developed using UV light exposure through the transparent substrate. A gate metal(s) is deposited on the exposed portions of the dielectric layer and the undeveloped portions of the photoresist. The undeveloped portions of the photoresist are removed along with portions of the gate metal over the source and drain regions to form a gate of the device on the dielectric layer over the channel material which is self-aligned to the source and drain electrodes.Type: GrantFiled: October 21, 2013Date of Patent: August 12, 2014Assignee: International Business Machines CorporationInventors: Wilfried Ernst-August Haensch, Zihong Liu
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Publication number: 20140117464Abstract: FinFET devices and methods for the fabrication thereof are provided. In one aspect, a method for fabricating a FET device includes the following steps. A wafer is provided having an active layer on an insulator. A plurality of fin hardmasks are patterned on the active layer. A dummy gate is placed over a central portion of the fin hardmasks. One or more doping agents are implanted into source and drain regions of the device. A dielectric filler layer is deposited around the dummy gate. The dummy gate is removed to form a trench in the dielectric filler layer. The fin hardmasks are used to etch a plurality of fins in the active layer within the trench. The doping agents are activated. A replacement gate is formed in the trench, wherein the step of activating the doping agents is performed before the step of forming the replacement gate.Type: ApplicationFiled: January 7, 2014Publication date: May 1, 2014Applicant: International Business Machines CorporationInventors: Josephine B. Chang, Michael A. Guillorn, Wilfried Ernst-August Haensch
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Publication number: 20140042393Abstract: Transistor devices having a self-aligned gate structure on transparent substrates and techniques for fabrication thereof are provided. In one aspect, a method of fabricating a transistor device includes the following steps. A channel material is formed on a transparent substrate. Source and drain electrodes are formed in contact with the channel material. A dielectric layer is deposited on the channel material. A photoresist is deposited on the dielectric layer and developed using UV light exposure through the transparent substrate. A gate metal(s) is deposited on the exposed portions of the dielectric layer and the undeveloped portions of the photoresist. The undeveloped portions of the photoresist are removed along with portions of the gate metal over the source and drain regions to form a gate of the device on the dielectric layer over the channel material which is self-aligned to the source and drain electrodes.Type: ApplicationFiled: October 21, 2013Publication date: February 13, 2014Applicant: International Business Machines CorporationInventors: Wilfried Ernst-August Haensch, Zihong Liu
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Patent number: 8637359Abstract: FinFET devices and methods for the fabrication thereof are provided. In one aspect, a method for fabricating a FET device includes the following steps. A wafer is provided having an active layer on an insulator. A plurality of fin hardmasks are patterned on the active layer. A dummy gate is placed over a central portion of the fin hardmasks. One or more doping agents are implanted into source and drain regions of the device. A dielectric filler layer is deposited around the dummy gate. The dummy gate is removed to form a trench in the dielectric filler layer. The fin hardmasks are used to etch a plurality of fins in the active layer within the trench. The doping agents are activated. A replacement gate is formed in the trench, wherein the step of activating the doping agents is performed before the step of forming the replacement gate.Type: GrantFiled: June 10, 2011Date of Patent: January 28, 2014Assignee: International Business Machines CorporationInventors: Josephine B. Chang, Michael A. Guillorn, Wilfried Ernst-August Haensch
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Patent number: 8569121Abstract: Transistor devices having a self-aligned gate structure on transparent substrates and techniques for fabrication thereof are provided. In one aspect, a method of fabricating a transistor device includes the following steps. A channel material is formed on a transparent substrate. Source and drain electrodes are formed in contact with the channel material. A dielectric layer is deposited on the channel material. A photoresist is deposited on the dielectric layer and developed using UV light exposure through the transparent substrate. A gate metal(s) is deposited on the exposed portions of the dielectric layer and the undeveloped portions of the photoresist. The undeveloped portions of the photoresist are removed along with portions of the gate metal over the source and drain regions to form a gate of the device on the dielectric layer over the channel material which is self-aligned to the source and drain electrodes.Type: GrantFiled: November 1, 2011Date of Patent: October 29, 2013Assignee: International Business Machines CorporationInventors: Wilfried Ernst-August Haensch, Zihong Liu
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Publication number: 20130105765Abstract: Transistor devices having a self-aligned gate structure on transparent substrates and techniques for fabrication thereof are provided. In one aspect, a method of fabricating a transistor device includes the following steps. A channel material is formed on a transparent substrate. Source and drain electrodes are formed in contact with the channel material. A dielectric layer is deposited on the channel material. A photoresist is deposited on the dielectric layer and developed using UV light exposure through the transparent substrate. A gate metal(s) is deposited on the exposed portions of the dielectric layer and the undeveloped portions of the photoresist. The undeveloped portions of the photoresist are removed along with portions of the gate metal over the source and drain regions to form a gate of the device on the dielectric layer over the channel material which is self-aligned to the source and drain electrodes.Type: ApplicationFiled: November 1, 2011Publication date: May 2, 2013Applicant: International Business Machines CorporationInventors: Wilfried Ernst-August Haensch, Zihong Liu
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Publication number: 20120313170Abstract: FinFET devices and methods for the fabrication thereof are provided. In one aspect, a method for fabricating a FET device includes the following steps. A wafer is provided having an active layer on an insulator. A plurality of fin hardmasks are patterned on the active layer. A dummy gate is placed over a central portion of the fin hardmasks. One or more doping agents are implanted into source and drain regions of the device. A dielectric filler layer is deposited around the dummy gate. The dummy gate is removed to form a trench in the dielectric filler layer. The fin hardmasks are used to etch a plurality of fins in the active layer within the trench. The doping agents are activated. A replacement gate is formed in the trench, wherein the step of activating the doping agents is performed before the step of forming the replacement gate.Type: ApplicationFiled: June 10, 2011Publication date: December 13, 2012Applicant: International Business Machines CorporationInventors: Josephine B. Chang, Michael A. Guillom, Wilfried Ernst-August Haensch
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Patent number: 8053317Abstract: Method of forming a semiconductor device which includes the steps of obtaining a semiconductor substrate having a logic region and an STI region; sequentially depositing layers of high K material, metal gate, first silicon and hardmask; removing the hardmask and first silicon layers from the logic region; applying a second layer of silicon on the semiconductor substrate such that the logic region has layers of high K material, metal gate and second silicon and the STI region has layers of high K material, metal gate, first silicon, hardmask and second silicon. There may also be a second hardmask layer between the metal gate layer and the first silicon layer in the STI region. There may also be a hardmask layer between the metal gate layer and the first silicon layer in the STI region but no hardmask layer between the first and second layers of silicon in the STI region.Type: GrantFiled: August 15, 2009Date of Patent: November 8, 2011Assignee: International Business Machines CorporationInventors: Satya N. Chakravarti, Dechao Guo, Wilfried Ernst-August Haensch, Pranita Kulkarni, Fei Liu, Philip J. Oldiges, Keith Kwong Hon Wong