Abstract: A time division multiplex communication system comprised of a plurality of modules, each module being equipped with a space division concentrator and a processor. The modules are interconnected by a control bus and by a plurality of speech busses, the number of speech busses being equal to the maximum number of modules. All busses are connected to each equipped module. The control bus is commonly connected to all modules and this bus is, in turn, controlled by a control circuit. In the control circuit, there is a flip-flop for each module for enabling a scanner in the control circuit to set the address of a module seeking use of the control bus. The processor in the module seeking service recognizes its address and transmits its call processing data on the control bus. Each speech bus is comprised of eight wires for parallel PCM bit transmission with time slot interchanging.