Abstract: A method utilizing a predetermined set of instructions in a wait routine reduces spurious signals caused by the power consumption of processors, particularly digital signal processors, which is dependent on the instruction code being executed. These spurious signals occur, for example, in processors performing cyclically recurring program routines which are initiated by interrupts where, during the run time of the routines, a first mean power consumption results, and where the run time of the program routines is shorter than the time between two successive interrupts. The cyclic changes in power consumption caused by this mode of operation of the digital signal processor are avoided by performing a wait routine between successive program routines which includes instructions selected to cause a mean power consumption of the processor during the wait routine to correspond to that during the program routines.

Abstract: A protective circuit for connecting contacts of monolithic integrated circuits, particularly CMOS input/output stages. The protective circuit has a four-layer device (ta, ts) with a defined switching threshold in the area of each connecting contact (A) and a low-resistivity current path (sa) from the connecting contact (A) to a supply terminal (VSS, VDD). The protective circuit also contains devices (zw2, z5) which prevent or provide a bypass for any undesired flow of current (i3, i4) between at least parts of the four-layer device and triggerable circuit regions (W2).

Abstract: The invention provides remote control methods and arrangements using pulse code modulation for transmission as in infrared remote control arrangements. A primary feature is that only one quartz oscillator is necessary and is used in the receiver part. The receiver measures the first pulse width transmitted and, dependent on that, defines the measure period of a control circuit. A further feature is that each remote control word is preceded by a prepulse and a postpulse with a threefold pulse width.

Abstract: A circuit arrangement for generating a pulse train having a predetermined first pulse spacing (a) and a second pulse spacing (b) differing from the first by an integral factor greater than one, which pulse spacings are assigned to the binary ZERO and the binary ONE, respectively, dependent upon a predetermined n-bit binary word.

Abstract: This relates to an MOS power stage of a two-phase clock signal generator arranged on the same integrated circuit chip as the circuit to be driven. The generator consists of one MOSFET inverter, the output of which is multiplexed by the two clock signals. In this manner, power loss in the MOSFET is reduced.