Abstract: A method as described for testing integrated circuits provided on a carrier. They comprise a series input (22) and a series output (24) for test and result patterns. A mode control register (30) is further present to receive a mode control signal train via the serial input. Under the control of said mode control signal train the serial input and output can be shortcircuited to each other, or further registers (32, 34, 36) can be selectively filled and emptied. In this manner, both the interior of the integrated circuit and respective interconnection functions can easily be tested by means of a universal protocol. Integrated circuits and the carrier only require minor extension/adaptations.

Abstract: A method for testing integrated circuits provided on a carrier. The circuits include a series input (22) and a series output (24) for test and result patterns. A mode control register (30) receives a mode control signal train via the serial input. Under the control of said mode control signal train the serial input and output can be shortcircuited to each other, or further registers (32, 34, 36) can be selectively filled and emptied. In this manner, both the interior of the integrated circuit and respective interconnection functions can easily be tested by a universal protocol. Integrated circuits and the carrier only require minor extension/adaptations.

Abstract: An electronic, digital IC module includes a substrate element on which is formed a test integrated circuit for the execution of a boundary scan on a standard integrated circuit formed on another substrate element. Either the substrate for the test circuit is provided in an electronic sub-module on which is formed a test socket, in which case the standard circuit is mounted piggy-back, or a hybrid package is provided composed of the two substrate elements which are interconnected by bond pads. The test circuit includes a shift register for parallel connection to the standard circuit and serial connection to an external test unit.

Abstract: A method of testing an interconnection function between two integrated circuits which are mounted on a carrier and which are interconnected by data connections, for example a printed wiring board, is disclosed. The integrated circuits are also connected to a serial bus via which test patterns and result patterns can be communicated between a test device which can be connected thereto and the respective integrated circuits. The bus of a preferred embodiment is formed by a so-called I.sup.2 C bus. In a further elaboration, this set-up can also be used for testing the internal logic circuitry of the integrated circuits. For the testing of the interconnection function, input/output cells with a parallel connection for performing the normal execution function in a transparent mode are provided. They also include series connections for communication test/result patterns by way of a shift register.

Abstract: A method of testing an interconnection function between two integrated circuits which are mounted on a carrier and which are interconnected by data connections, for example a printed wiring board, is disclosed. The integrated circuits are also connected to a serial bus via which test patterns and result patterns can be communicated between a test device which can be connected thereto and the respective integrated circuits. The bus of a preferred embodiment is formed by a so-called I.sup.2 C bus. In a further elaboration, this set-up can also be used for testing the internal logic circuitry of the integrated circuits. For the testing of the interconnection function, input/output cells with a parallel connection for performing the normal execution function in a transparent mode are provided. They also include series connections for communication test/result patterns by way of a shift register.