Abstract: An optical network unit useful in a passive optical network has capability for automatic shutdown upon detection of a malfunction, thereby protecting the integrity of upstream data transmitted in the network. The unit detects the generation of upstream light during intervals in which transmission is not authorized. In response, the light source of the unit is deactivated to prevent collisions with upstream data from other optical network units in the network.

Abstract: A clock and data recovery circuit and method are used in a digital data communications system. The circuit and method are effectively employed for high speed, burst-mode transmission and allow rapid recovery of the clock and data signals without the need for an extended header, and notwithstanding the presence of substantial timing jitter. The method adaptively selects from among three delay times for the extraction of data by identifying a frequently recurring incoming pattern in the incoming data. The delay time is selected in a manner that insures that the same pattern is present in the reconstructed, resynchronized output data.

Abstract: An optical network unit useful in a passive optical network has capability for automatic shutdown upon detection of a malfunction, thereby protecting the integrity of upstream data transmitted in the network. The unit detects the generation of upstream light during intervals in which transmission is not authorized. In response, the light source of the unit is deactivated to prevent collisions with upstream data from other optical network units in the network.

Abstract: A clock and data recovery circuit and method are used in a digital data communications system. The circuit and method are effectively employed for high speed, burst-mode transmission and allow rapid recovery of the clock and data signals without the need for an extended header, and notwithstanding the presence of substantial timing jitter. The method adaptively selects from among three delay times for the extraction of data by identifying a frequently recurring incoming pattern in the incoming data. The delay time is selected in a manner that insures that the same pattern is present in the reconstructed, resynchronized output data.

Abstract: The output frequency of a simple low-power-dissipation oscillator circuit designed to drive PPS CMOS circuits is controlled by a closed-loop system. In response to deviations of the output frequency from a prescribed value, the system generates correction signals that are applied to an array of capacitors. In that way, capacitance is electrically added to or subtracted from a series-resonant path of the oscillator circuit, thereby to automatically establish and maintain the output frequency of the circuit at or near its prescribed value.

Abstract: In low-power-dissipation CMOS circuitry, conventional CMOS inverters are powered by a repetitively ramped power supply. Clock signals are needed in the circuitry for controlling data flow therein. To ensure optimal low-power operation of the circuitry, clock signals are derived directly from the ramped power supply waveform itself. Additionally, a technique similar to that employed in the clock-signal-generating arrangement is utilized to propagate digital data signals between chips in a low-power way.